Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms

Abstract

Cryptographic hardware accelerators and root-of-trust circuits like True-Random-Number-Generators (TRNG) and Physically-Unclonable-Functions (PUF) have become essential components of present-day secure platforms. These circuits provide an on-die boundary within which users are given assurances that data privacy and integrity is preserved during computations and transport between storage and compute elements. The focus of hardware security engineers over the past many years has been in improving performance while reducing area and power consumption of cryptographic circuits. This tidy scenario was disrupted by a spate of attacks on computing platforms reported in the past few years. These attacks employed techniques such as speculative side-channels, physical (power/electromagnetic) side-channels, voltage/clock glitching and fault-injection to extract embedded secrets such as encryption keys or access privileged sections of system memory. The security community has responded to these attacks by launching research in resilient architectures and security circuits that are resistant to physical/machine-learning attacks. This talk will discuss attack-resistant encryption circuits for popular encryption workloads such as AES and RSA as well as describe PUF circuits that are resilient to powerful machine-learning attacks. While these circuits are shown to be secure against known attacks today, attackers are getting increasingly sophisticated with high resolution probes and employing advanced machine-learning techniques to subvert protection mechanisms. Security hardware designers are therefore engaged in an arms race of constantly outwitting malicious attackers while relying on continued research in energy-efficient attack-resistant security circuits.