In the analog domain, with the increase in ReRAM m × n crossbar array, the Loading Effect (LE) seems to grow at the input of the comparator stage in analog to digital converter (ADC). The reference voltage generating ladder nodes for ADC are susceptible to design parameters due to small input voltages. We used the PMOS transistor to design this ladder circuitry. Further, sleep mode is applied using the power-gating (PG) technique to lower power dissipation. In this article, a Pareto study has been performed to evaluate robust and stable circuitry with minimum LE in the reference voltage ladder for ADC. An NMOS-based Current mirror is also designed and used with the proposed reference voltage ladder to achieve better stability in terms of power supply and reference voltage variations. Further, we analyzed the Process, Voltage, and Temperature (PVT) variation impact on the proposed circuitry. Finally, the power consumption of the proposed ladder at the 180nm technology node, is 0.7uW. Also, the circuit supports the power-gating technique in sleep mode, saving 43% of total power. Circuit's Monte-Carlo simulation for node voltage variation shows minimum mean and σ deviation. The circuit supports the power-gating technique in sleep mode, saving 43% of total power.
{"title":"Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array","authors":"Varun Bhatnagar, Gopal R. Raut, S. Vishvakarma","doi":"10.1145/3526241.3530354","DOIUrl":"https://doi.org/10.1145/3526241.3530354","url":null,"abstract":"In the analog domain, with the increase in ReRAM m × n crossbar array, the Loading Effect (LE) seems to grow at the input of the comparator stage in analog to digital converter (ADC). The reference voltage generating ladder nodes for ADC are susceptible to design parameters due to small input voltages. We used the PMOS transistor to design this ladder circuitry. Further, sleep mode is applied using the power-gating (PG) technique to lower power dissipation. In this article, a Pareto study has been performed to evaluate robust and stable circuitry with minimum LE in the reference voltage ladder for ADC. An NMOS-based Current mirror is also designed and used with the proposed reference voltage ladder to achieve better stability in terms of power supply and reference voltage variations. Further, we analyzed the Process, Voltage, and Temperature (PVT) variation impact on the proposed circuitry. Finally, the power consumption of the proposed ladder at the 180nm technology node, is 0.7uW. Also, the circuit supports the power-gating technique in sleep mode, saving 43% of total power. Circuit's Monte-Carlo simulation for node voltage variation shows minimum mean and σ deviation. The circuit supports the power-gating technique in sleep mode, saving 43% of total power.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present a comprehensive analysis of explainability of Neural Network (NN) models in the context of power Side-Channel Analysis (SCA), to gain insight into which features or Points of Interest (PoI) contribute the most to the classification decision. Although many existing works claim state-of-the-art accuracy in recovering secret key from cryptographic implementations, it remains to be seen whether the models actually learn representations from the leakage points. In this work, we evaluated the reasoning behind the success of a NN model, by validating the relevance scores of features derived from the network to the ones identified by traditional statistical PoI selection methods. Thus, utilizing the explainability techniques as a standard validation technique for NN models is justified.
{"title":"Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis","authors":"Anupam Golder, Ashwin Bhat, A. Raychowdhury","doi":"10.1145/3526241.3530346","DOIUrl":"https://doi.org/10.1145/3526241.3530346","url":null,"abstract":"In this work, we present a comprehensive analysis of explainability of Neural Network (NN) models in the context of power Side-Channel Analysis (SCA), to gain insight into which features or Points of Interest (PoI) contribute the most to the classification decision. Although many existing works claim state-of-the-art accuracy in recovering secret key from cryptographic implementations, it remains to be seen whether the models actually learn representations from the leakage points. In this work, we evaluated the reasoning behind the success of a NN model, by validating the relevance scores of features derived from the network to the ones identified by traditional statistical PoI selection methods. Thus, utilizing the explainability techniques as a standard validation technique for NN models is justified.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122677335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryptographic hardware accelerators and root-of-trust circuits like True-Random-Number-Generators (TRNG) and Physically-Unclonable-Functions (PUF) have become essential components of present-day secure platforms. These circuits provide an on-die boundary within which users are given assurances that data privacy and integrity is preserved during computations and transport between storage and compute elements. The focus of hardware security engineers over the past many years has been in improving performance while reducing area and power consumption of cryptographic circuits. This tidy scenario was disrupted by a spate of attacks on computing platforms reported in the past few years. These attacks employed techniques such as speculative side-channels, physical (power/electromagnetic) side-channels, voltage/clock glitching and fault-injection to extract embedded secrets such as encryption keys or access privileged sections of system memory. The security community has responded to these attacks by launching research in resilient architectures and security circuits that are resistant to physical/machine-learning attacks. This talk will discuss attack-resistant encryption circuits for popular encryption workloads such as AES and RSA as well as describe PUF circuits that are resilient to powerful machine-learning attacks. While these circuits are shown to be secure against known attacks today, attackers are getting increasingly sophisticated with high resolution probes and employing advanced machine-learning techniques to subvert protection mechanisms. Security hardware designers are therefore engaged in an arms race of constantly outwitting malicious attackers while relying on continued research in energy-efficient attack-resistant security circuits.
{"title":"Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms","authors":"S. Mathew","doi":"10.1145/3526241.3530053","DOIUrl":"https://doi.org/10.1145/3526241.3530053","url":null,"abstract":"Cryptographic hardware accelerators and root-of-trust circuits like True-Random-Number-Generators (TRNG) and Physically-Unclonable-Functions (PUF) have become essential components of present-day secure platforms. These circuits provide an on-die boundary within which users are given assurances that data privacy and integrity is preserved during computations and transport between storage and compute elements. The focus of hardware security engineers over the past many years has been in improving performance while reducing area and power consumption of cryptographic circuits. This tidy scenario was disrupted by a spate of attacks on computing platforms reported in the past few years. These attacks employed techniques such as speculative side-channels, physical (power/electromagnetic) side-channels, voltage/clock glitching and fault-injection to extract embedded secrets such as encryption keys or access privileged sections of system memory. The security community has responded to these attacks by launching research in resilient architectures and security circuits that are resistant to physical/machine-learning attacks. This talk will discuss attack-resistant encryption circuits for popular encryption workloads such as AES and RSA as well as describe PUF circuits that are resilient to powerful machine-learning attacks. While these circuits are shown to be secure against known attacks today, attackers are getting increasingly sophisticated with high resolution probes and employing advanced machine-learning techniques to subvert protection mechanisms. Security hardware designers are therefore engaged in an arms race of constantly outwitting malicious attackers while relying on continued research in energy-efficient attack-resistant security circuits.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network pruning can effectively alleviate the excessive parameters and computation issues in CNNs. However, unstructured pruning is not hardware friendly, while structured pruning will result in a significant loss of accuracy. In this paper, an unstructured fine-grained pruning strategy is proposed and achieves a 16X compression ratio with a top-1 accuracy loss of 1.4% for VGG-16. Combined with the proposed hardware-oriented hyperparameter selection method, compression rates of up to 64X can be obtained while fully meeting the edge-side accuracy requirements. Further, a light-weight, high-performance sparse CNN accelerator with modified systolic array is proposed for pruned VGG-16. The experimental results show that compared with the most advanced design, the proposed accelerator can achieve 21 Frames Per Second (FPS) with 3X better power efficiency and 2.19X better calculation density.
{"title":"Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy","authors":"Tianyang Yu, Bi Wu, Ke Chen, C. Yan, Weiqiang Liu","doi":"10.1145/3526241.3530318","DOIUrl":"https://doi.org/10.1145/3526241.3530318","url":null,"abstract":"Network pruning can effectively alleviate the excessive parameters and computation issues in CNNs. However, unstructured pruning is not hardware friendly, while structured pruning will result in a significant loss of accuracy. In this paper, an unstructured fine-grained pruning strategy is proposed and achieves a 16X compression ratio with a top-1 accuracy loss of 1.4% for VGG-16. Combined with the proposed hardware-oriented hyperparameter selection method, compression rates of up to 64X can be obtained while fully meeting the edge-side accuracy requirements. Further, a light-weight, high-performance sparse CNN accelerator with modified systolic array is proposed for pruned VGG-16. The experimental results show that compared with the most advanced design, the proposed accelerator can achieve 21 Frames Per Second (FPS) with 3X better power efficiency and 2.19X better calculation density.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123818056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Logic locking is a technique for the protection of hardware intellectual property (IP) from malicious entities like piracy, overproduction, reverse engineering, etc. The register transfer level (RTL) locking performs the locking on RTL description for protection of the IP even from the early design cycle. TAO [12] is such a locking scheme that employs locking during the high-level synthesis (HLS) process. In this paper, we evaluate the unlocking capability of the genetic algorithm (GA) by performing attacks on the RTLs locked using TAO based technique. We demonstrate the ability of GA to unlock TAO generated RTLs in seconds. Our GA based attack is faster as compared to the Satisfiability Modulo Theories (SMT) based attack [9]. The GA based method also converges well in most of the cases as shown in the experimental results.
{"title":"GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking","authors":"Gagan Gayari, C. Karfa, P. Guha","doi":"10.1145/3526241.3530362","DOIUrl":"https://doi.org/10.1145/3526241.3530362","url":null,"abstract":"Logic locking is a technique for the protection of hardware intellectual property (IP) from malicious entities like piracy, overproduction, reverse engineering, etc. The register transfer level (RTL) locking performs the locking on RTL description for protection of the IP even from the early design cycle. TAO [12] is such a locking scheme that employs locking during the high-level synthesis (HLS) process. In this paper, we evaluate the unlocking capability of the genetic algorithm (GA) by performing attacks on the RTLs locked using TAO based technique. We demonstrate the ability of GA to unlock TAO generated RTLs in seconds. Our GA based attack is faster as compared to the Satisfiability Modulo Theories (SMT) based attack [9]. The GA based method also converges well in most of the cases as shown in the experimental results.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130878523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Maze routing remains the most time-consuming step for modern global routers. Previous works accelerate the maze routing by routing multiple regions or nets simultaneously. This paper presents a novel parallel maze router with bidirectional path search and dynamic routing scheduling, which exhibits higher efficiency than all the previous routers. On the ISPD 2008 benchmark suite, our router outperforms the fastest global routers SPRoute and FastRoute 4.1 by an average speedup of 1.95x and 10.03x, while the difference on the total overflow and wirelength is negligible.
{"title":"An Efficient Maze Routing Algorithm for Fast Global Routing","authors":"Zhaoqi Fu, Wenxin Yu, Jie Ma, Xin Cheng","doi":"10.1145/3526241.3530360","DOIUrl":"https://doi.org/10.1145/3526241.3530360","url":null,"abstract":"Maze routing remains the most time-consuming step for modern global routers. Previous works accelerate the maze routing by routing multiple regions or nets simultaneously. This paper presents a novel parallel maze router with bidirectional path search and dynamic routing scheduling, which exhibits higher efficiency than all the previous routers. On the ISPD 2008 benchmark suite, our router outperforms the fastest global routers SPRoute and FastRoute 4.1 by an average speedup of 1.95x and 10.03x, while the difference on the total overflow and wirelength is negligible.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optimization means finding the best possible solution to a given problem -- but challenges of scale and complexity keep many real-world optimization needs beyond reach. The Institute for Learning-enabled Optimization at Scale (TILOS) is a new National AI Research Institute led by UC San Diego in partnership with MIT, National University, Penn, UT Austin and Yale. TILOS is sponsored by the U.S. National Science Foundation, with partial support from Intel Corporation. The TILOS mission: make impossible optimizations possible, at scale and in practice. This talk introduces TILOS, its research agenda, and how it aims to establish a "national nexus" of AI and machine learning, optimization, and use domains that include integrated-circuit design and design automation. The talk will point out directions along which the interplay of learning and optimization can boost the scaling and quality of EDA outcomes.
{"title":"AI/ML, Optimization and EDA in the TILOS AI Research Institute","authors":"A. Kahng","doi":"10.1145/3526241.3530052","DOIUrl":"https://doi.org/10.1145/3526241.3530052","url":null,"abstract":"Optimization means finding the best possible solution to a given problem -- but challenges of scale and complexity keep many real-world optimization needs beyond reach. The Institute for Learning-enabled Optimization at Scale (TILOS) is a new National AI Research Institute led by UC San Diego in partnership with MIT, National University, Penn, UT Austin and Yale. TILOS is sponsored by the U.S. National Science Foundation, with partial support from Intel Corporation. The TILOS mission: make impossible optimizations possible, at scale and in practice. This talk introduces TILOS, its research agenda, and how it aims to establish a \"national nexus\" of AI and machine learning, optimization, and use domains that include integrated-circuit design and design automation. The talk will point out directions along which the interplay of learning and optimization can boost the scaling and quality of EDA outcomes.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115480278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi
With the progressive innovation of VLSI technology, Tiled Chip Multicore Processors (TCMP) have surfaced up as the backbone of the modern data intensive parallel multi-core systems. Network-on-Chip (NoC) is considered as the most preferred choice for on-chip communication. Manufacturers have begun to investigate the prospects of using third-party IP in sophisticated TCMP designs due to strict time-to-market limitations. The inflated reliance over third party IPs induced security vulnerabilities in inter-tile communication. In this paper, we implement a novel Hardware Trojan (HT) called as Delay Trojan (DT) placed in an NoC router. Proposed DT adds random delay to flits going through it, while other NoC routers merely experience regular congestion, making DT detection difficult. As a result, packets of latency-critical applications stalls impacting system performance and throughput. Further, we propose a dynamic adaptive learning framework embedded in NoC routers that detects DT with reasonable accuracy and alerts neighboring routers. We also propose a caging technique to re-route packets. Our experimental study evaluates the impact of DT and the effectiveness of the proposed solution.
{"title":"Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging","authors":"Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi","doi":"10.1145/3526241.3530333","DOIUrl":"https://doi.org/10.1145/3526241.3530333","url":null,"abstract":"With the progressive innovation of VLSI technology, Tiled Chip Multicore Processors (TCMP) have surfaced up as the backbone of the modern data intensive parallel multi-core systems. Network-on-Chip (NoC) is considered as the most preferred choice for on-chip communication. Manufacturers have begun to investigate the prospects of using third-party IP in sophisticated TCMP designs due to strict time-to-market limitations. The inflated reliance over third party IPs induced security vulnerabilities in inter-tile communication. In this paper, we implement a novel Hardware Trojan (HT) called as Delay Trojan (DT) placed in an NoC router. Proposed DT adds random delay to flits going through it, while other NoC routers merely experience regular congestion, making DT detection difficult. As a result, packets of latency-critical applications stalls impacting system performance and throughput. Further, we propose a dynamic adaptive learning framework embedded in NoC routers that detects DT with reasonable accuracy and alerts neighboring routers. We also propose a caging technique to re-route packets. Our experimental study evaluates the impact of DT and the effectiveness of the proposed solution.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bounded transparent-scan supports test compaction beyond that achievable with conventional scan-based tests. This article considers the compression of bounded transparent-scan tests. All the components of a test (scan-in state, primary input vector, scan-in and scan-enable sequences) are produced by the on-chip decompression logic from a compressed test. The article describes a test compaction procedure that starts from a conventional compressed and compacted multicycle scan-based test set. Such a test set benefits from test data compression and test compaction applicable to conventional scan-based tests. The procedure modifies as many tests as possible into compressed bounded transparent-scan tests to reduce the number of tests, the storage requirements, and the number of clock cycles required for test application. Experimental results for benchmark circuits demonstrate the ability to compress bounded transparent-scan tests and achieve test compaction.
{"title":"Compaction of Compressed Bounded Transparent-Scan Test Sets","authors":"I. Pomeranz","doi":"10.1145/3526241.3530358","DOIUrl":"https://doi.org/10.1145/3526241.3530358","url":null,"abstract":"Bounded transparent-scan supports test compaction beyond that achievable with conventional scan-based tests. This article considers the compression of bounded transparent-scan tests. All the components of a test (scan-in state, primary input vector, scan-in and scan-enable sequences) are produced by the on-chip decompression logic from a compressed test. The article describes a test compaction procedure that starts from a conventional compressed and compacted multicycle scan-based test set. Such a test set benefits from test data compression and test compaction applicable to conventional scan-based tests. The procedure modifies as many tests as possible into compressed bounded transparent-scan tests to reduce the number of tests, the storage requirements, and the number of clock cycles required for test application. Experimental results for benchmark circuits demonstrate the ability to compress bounded transparent-scan tests and achieve test compaction.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128736624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a technique called CoSeP that combines the effect of compression and the content of the compressed blocks to reduce bit-flips in the encrypted PCM-based main memories. The blocks are compressed using the technique (out of FPC, BDI, and COMF) that offers minimum block size when the sizes of the two smallest compressed blocks are non-similar. However, for compressed blocks of similar sizes, the block is compressed using the technique that encounters minimum bit-flips, which reduces bit-flips further. Experimental results show that our technique gives a substantial reduction in bit-flips and improvements in lifetime compared to baseline and state-of-the-art techniques.
{"title":"CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories","authors":"Arijit Nath, H. Kapoor","doi":"10.1145/3526241.3530375","DOIUrl":"https://doi.org/10.1145/3526241.3530375","url":null,"abstract":"In this paper, we propose a technique called CoSeP that combines the effect of compression and the content of the compressed blocks to reduce bit-flips in the encrypted PCM-based main memories. The blocks are compressed using the technique (out of FPC, BDI, and COMF) that offers minimum block size when the sizes of the two smallest compressed blocks are non-similar. However, for compressed blocks of similar sizes, the block is compressed using the technique that encounters minimum bit-flips, which reduces bit-flips further. Experimental results show that our technique gives a substantial reduction in bit-flips and improvements in lifetime compared to baseline and state-of-the-art techniques.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129127185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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