Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits

Abstract

Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4 demultiplexer circuits on the top of liquid ion-trap realizable 1x1 and Muthukrishnan-Stroud gates. Then we show scalable architectures for design of mx1 multiplexer and 1xm demultiplexer circuits using 4x1 multiplexers and 1x4 demultiplexers, respectively, where m ≤ 4n and n is the number of selection inputs. The proposed realizations of reversible multiplexer and demultiplexer circuits are more efficient than the earlier realizations in terms of number of primitive gates and number of ancilla inputs required.