Design and optimization of a low-power and very-high-performance 0.25-/spl mu/m advanced PNP bipolar process

B. Djezzar
{"title":"Design and optimization of a low-power and very-high-performance 0.25-/spl mu/m advanced PNP bipolar process","authors":"B. Djezzar","doi":"10.1109/SMICND.1996.557309","DOIUrl":null,"url":null,"abstract":"Low-power and very-high-performance 0.25-/spl mu/m vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator.","PeriodicalId":266178,"journal":{"name":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.1996.557309","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Low-power and very-high-performance 0.25-/spl mu/m vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
低功耗高性能0.25-/spl mu/m先进PNP双极工艺的设计与优化
采用混合二维数值器件/电路模拟器(CODECS),设计了低功耗、高性能的0.25-/spl mu/m垂直PNP双极工艺。该PNP晶体管具有25nm宽的发射极,38nm宽的基极区域,17的电流增益(无多晶硅发射极效应),最大截止频率为24ghz。该PNP晶体管设计的传统ECL电路在1.75 mw时具有22ps的空载栅极延迟,且空载ECL环形振荡器的延迟时间小于16ps /级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
High-level synthesis of an enhanced Connex memory Aluminum nitride films for optical applications Microstructures for arrays of chemical gas sensors The nature of M-InP contacts aging Monte Carlo hardware simulator for electron dynamics in semiconductors
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1