System-level simulator for process variation influenced synchronous and asynchronous NoCs

Abstract

System-Level simulator is proposed to determine the ability of synchronous and asynchronous NoCs to alleviate the process variation effect. Throughput variation and different delay components variation are provided by the newly developed framework. System-Level simulation shows similarities with circuit-level simulation in terms of behavior and performance variation trend when moving from one technology node to another. Clock skew significantly degrades synchronous NoCs performance. Clock skew is more obvious with process variation. Despite the handshaking overhead, asynchronous NoC may be more immune to process variation than synchronous networks. PV-aware routing algorithm reduces the performance degradation to 8.3% and 11.4% for 45nm and 32nm asynchronous NoCs respectively. Using different traffic workloads and PV-unaware routing algorithm, synchronous networks lose on average 17.7% and 27.8% of nominal throughput for 45nm and 32nm technologies, respectively due to process variation. Whereas, asynchronous NoC throughput degradation is about 7.4% and 11.5% for 45nm and 32nm, respectively. In addition to technology scaling, NoC scaling also affects the throughput degradation. 256-core NoC shows the highest throughput degradation of 16% and 22% for asynchronous NoC for 45nm and 32nm technologies respectively.