Extended data retention characteristics after more than 10/sup 4/ write and erase cycles in EEPROMs

Abstract

Improvements in data retention characteristics of a FETMOS cell which has a self-aligned double poly-Si stacked structure are discussed. The improvement results from the use of a uniform write and erase technology. Experiments show that a gradual detrapping of electrons from the gate oxide to the substrate effectively suppresses data loss of the erased cell which stores positive charges in the floating gate. It is also shown that a uniform write and uniform erase technology using Fowler-Nordheim tunneling current guarantees a wide cell threshold voltage window even after 10/sup 6/ write and erase cycles. This technology realizes a highly reliable EEPROM with extended data retention characteristics.<>