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28th Annual Proceedings on Reliability Physics Symposium最新文献

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Evolution of VLSI reliability engineering VLSI可靠性工程的发展
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66052
D. Crook
Projection indicates that by the turn of the century microcomputer chips will have 100 million transistors and failure rates of less than 10 FIT. Traditional accelerated product life tests and wafer-level reliability measurement techniques presently being developed will have severe limitations in resolving the 10 FIT failure rate of complex VLSI circuits. These limitations are discussed, along with the change in direction that the reliability engineering and manufacturing community will have to take over the next decade to meet the challenge of continuously decreasing failure rate goals.<>
预测表明,到本世纪初,微型计算机芯片将有1亿个晶体管,故障率将低于10 FIT。目前正在开发的传统加速产品寿命测试和晶圆级可靠性测量技术在解决复杂VLSI电路的10 FIT故障率方面存在严重局限性。讨论了这些限制,以及可靠性工程和制造社区在未来十年必须采取的方向变化,以应对不断降低故障率目标的挑战。
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引用次数: 80
Improvement of electromigration resistance of layered aluminum conductors 提高层状铝导体的电迁移电阻
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66056
K. Hinode, Y. Homma
The electromigration of layered fine Al conductors (AlSi/TiN, AlSi/W, over/under) is discussed. The study indicates that (1) layering with refractory metals degrades the migration immunity of the Al layer, (2) refractory metal layers tend to suppress Al grain growth and crystal orientation, (3) by improving the film properties of refractory metals and optimizing the layer structure to minimize this grain growth suppression, conductor lifetimes can be lengthened by one or more orders of magnitude over those of conventionally layered or monolayer conductors.<>
讨论了层状精细铝导体(AlSi/TiN, AlSi/W,上/下)的电迁移问题。研究表明:(1)难熔金属层会降低Al层的迁移抗扰性;(2)难熔金属层会抑制Al晶粒生长和晶体取向;(3)通过改善难熔金属的薄膜性能和优化层结构来最小化这种晶粒生长抑制,导体的寿命可以比传统的层状或单层导体延长一个或多个数量级。
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引用次数: 14
Step spacing effects on electromigration 步距对电迁移的影响
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66055
A. Oates
Step spacing effects on electromigration in second-level runners of a two-level metal technology are investigated by stressing test structures with a wide range of spacing, of severe topography. Metal step coverage is affected by step spacing, and it is shown that regions with poor coverage (10, 20%) are particularly vulnerable to electromigration failure. When the interlevel dielectric processing is changed to improve step coverage, metal lifetimes do not increase to the extent expected. A new mode that occurs within a specific range of step spacing appears to dominate failure.<>
采用大间距、高地形条件下的应力试验结构,研究了台阶间距对二级流道电迁移的影响。金属台阶覆盖受到台阶间距的影响,并且表明覆盖率较低的区域(10,20%)特别容易发生电迁移失败。当改变层间介电处理以提高阶跃覆盖率时,金属寿命并没有增加到预期的程度。出现在特定步距范围内的一种新模式似乎主导了失效
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引用次数: 4
Extended data retention characteristics after more than 10/sup 4/ write and erase cycles in EEPROMs eeprom中超过10/sup / 4/写和擦除周期后的扩展数据保留特性
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66097
S. Aritome, R. Kirisawa, T. Endoh, R. Nakayama, R. Shirota, K. Sakui, K. Ohuchi, F. Masuoka
Improvements in data retention characteristics of a FETMOS cell which has a self-aligned double poly-Si stacked structure are discussed. The improvement results from the use of a uniform write and erase technology. Experiments show that a gradual detrapping of electrons from the gate oxide to the substrate effectively suppresses data loss of the erased cell which stores positive charges in the floating gate. It is also shown that a uniform write and uniform erase technology using Fowler-Nordheim tunneling current guarantees a wide cell threshold voltage window even after 10/sup 6/ write and erase cycles. This technology realizes a highly reliable EEPROM with extended data retention characteristics.<>
讨论了自对准双多晶硅堆叠结构的femos电池的数据保留特性的改进。这种改进是由于使用了统一的写入和擦除技术。实验表明,从栅极氧化物到衬底的电子逐渐脱陷,有效地抑制了在浮栅中存储正电荷的擦除电池的数据丢失。研究还表明,使用Fowler-Nordheim隧道电流的均匀写入和均匀擦除技术即使在10/sup / 6/写入和擦除周期后也能保证宽的电池阈值电压窗口。该技术实现了具有扩展数据保留特性的高可靠性EEPROM。
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引用次数: 13
Measurement of three dimensional stress and modeling of stress induced migration failure in aluminium interconnects 铝互连体三维应力测量及应力诱发迁移破坏模型
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66090
A. Tezaki, T. Mineta, H. Egawa, T. Noguchi
Stress-induced migration failure in fine aluminium interconnects is explained by measurements of mechanical stress and a kinetic failure model. An advanced stress-measurement method using X-ray diffractometry revealed the actual three-dimensional mechanical stresses and open failure test results were well correlated in terms of the covering insulator, metal linewidth, test temperature, and time-dependent relaxation profile. A kinetic model, successfully reproduced the non-Arrhenius behavior of the failure rate under various parameters. An exponent of 4 and an activation energy of 1.0-1.4 eV were obtained. The microscopic mechanism of stress migration along with stress relaxation, and the practical advantage of the modeling are discussed.<>
通过机械应力测量和动力学破坏模型解释了细铝互连中应力诱发的迁移破坏。一种先进的x射线衍射应力测量方法表明,实际的三维机械应力与开放破坏测试结果在覆盖绝缘体、金属线宽、测试温度和随时间变化的松弛曲线方面具有良好的相关性。一个动力学模型,成功地再现了故障率在不同参数下的非阿伦尼乌斯行为。得到了4的指数和1.0 ~ 1.4 eV的活化能。讨论了应力随应力松弛迁移的微观机理,以及该模型的实用价值。
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引用次数: 31
Distribution phenomena of charged defects and neutral electron traps in process-induced radiation-damaged IGFETs with gate insulators grown at 1000 degrees C and 800 degrees C 在1000℃和800℃生长栅绝缘体的过程诱导辐射损伤igfet中带电缺陷和中性电子陷阱的分布现象
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66075
M. Walters, A. Reisman
Gate oxide defects, in the form of trapped charges and neutral electron traps, were measured before and after irradiation using optically assisted electron injection. Following irradiation and injection, the measured voltage shifts ( Delta V/sub T/) indicate that radiation-induced extrinsic defects are localized near, but not exactly at the Si-SiO/sub 2/ interface. Delta V/sub T/ is found to be linear with respect to the gate oxide thickness when the top electrode resides above the defect region, and quadratic with respect to the thickness when the top electrode encroaches on the defect region. For very thin gate oxides, Delta V/sub T/ approaches zero. Application of a defect distribution model based on this behavior reveals that the gate oxidation temperature does not influence the distribution of radiation-induced defects, but does influence their concentration; with the 800 degrees C oxides always containing more defects than the 1000 degrees C oxides. A gate oxide thickness regime of less than 5-6 nm in which radiation-induced threshold voltage shifts approach zero is identified.<>
用光学辅助电子注入法测量了辐照前后的栅极氧化缺陷,其形式为捕获电荷和中性电子陷阱。在辐照和注入后,测量到的电压位移(δ V/sub T/)表明,辐射诱发的外源缺陷定位在Si-SiO/sub 2/界面附近,而不是完全定位在Si-SiO/sub 2/界面。当顶电极位于缺陷区域上方时,δ V/sub T/与栅氧化层厚度成线性关系,当顶电极侵入缺陷区域时,δ V/sub T/与栅氧化层厚度成二次关系。对于很薄的栅极氧化物,V/ T/趋近于零。基于该特性的缺陷分布模型的应用表明,栅极氧化温度不影响辐射缺陷的分布,但会影响辐射缺陷的浓度;800摄氏度的氧化物总是比1000摄氏度的氧化物含有更多的缺陷。确定了小于5-6 nm的栅极氧化物厚度范围,其中辐射诱导的阈值电压位移接近零。
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引用次数: 0
Current density dependence of electromigration t/sub 50/ enhancement due to pulsed operation 脉冲操作引起的电迁移电流密度依赖性t/sub - 50/增强
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66071
J. Suehle, H. Schafft
Two effects that complicate the electromigration characterization of metallization for pulsed stress are discussed. One is the dependence of the t/sub 50/ enhancement (due to pulsed operation) on current density, and the other is a decrease of this enhancement over a range of frequencies (0.2 to 2 MHz) that is connected with the Joule heating. These effects are discussed in terms of changes in the buildup and relaxation response times of the excess vacancy concentrations.<>
讨论了使脉冲应力下金属化电迁移表征复杂化的两个影响因素。一个是t/sub 50/增强(由于脉冲操作)对电流密度的依赖,另一个是在与焦耳加热相关的频率范围内(0.2至2 MHz)这种增强的降低。这些影响是根据多余空位浓度的累积和弛豫响应时间的变化来讨论的。
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引用次数: 9
Electrical measurements of moisture penetration through passivation 通过钝化对水分渗透的电测量
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66065
C. Shirley, S.C. Maston
The low-frequency (10 KHz) dissipation factor of metal comb/serpentine structures sandwiched between a phosphosilicate glass (PSG) substrate and passivation is a useful electrical indication of moisture penetration through the passivation. Wafer-level dissipation factor readouts after periods of highly accelerated temperature/humidity stress technique (HAST) testing at 159 degrees C and 85% relative humidity were used to monitor the rate of moisture ingression through passivations of various compositions and thicknesses. For plasma-deposited oxynitride films the dominant mechanism is uniform penetration (intrinsic) with a median-time-to-failure of 370 hours (at 159/85). For oxynitride films capped by nitride films, the dominant mechanism is penetration through defects in the nitride film. The defect density of nitride cap films increases with decreasing nitride film thickness.<>
夹在磷硅酸盐玻璃(PSG)衬底和钝化之间的金属梳状/蛇形结构的低频(10 KHz)耗散因子是一种有用的电学指示,表明水分通过钝化渗透。在159℃和85%的相对湿度下进行高加速温度/湿度应力技术(HAST)测试后,晶圆级耗散系数读数用于监测不同成分和厚度的钝化过程中水分的侵入率。对于等离子沉积的氮化氧薄膜,主要机制是均匀渗透(内在),平均失效时间为370小时(159/85)。对于被氮化膜覆盖的氮化氧薄膜,主要机理是穿透氮化膜中的缺陷。氮化膜的缺陷密度随氮化膜厚度的减小而增大
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引用次数: 4
Thermal breakdown of VLSI by ESD pulses 用ESD脉冲热击穿VLSI
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66101
D. Lin
A three-dimensional thermal model to determine the temperature rise and voltage build-up of VLSI devices stressed by human-body model (HBM) electrostatic discharges (ESD) is discussed. Application of the model to a specific device is yields failure thresholds and failure sites in agreement with the experimental results. This detailed model can be used to evaluate and improve designs of ESD protection circuits. It not only reconfirms the good design principles for ESD protection circuits, but also points out the importance of pulse risetime in determining the failure site. Allowing a wide range in risetime in ESD simulator specifications (such as the 0-10 ns range in MIL-STD Method 3015.6 Notice 7 and the 2-10 ns range in the EOS/ESD Association HBM Standard), may cause ESD pulses of different risetimes within the allowable range to deposit energy to different spots in a device and yield uncorrelatable ESD thresholds.<>
讨论了人体模型静电放电(ESD)作用下超大规模集成电路器件温升和电压累积的三维热模型。将该模型应用于具体装置,得到了与实验结果一致的失效阈值和失效点。该详细模型可用于评估和改进ESD保护电路的设计。这不仅再次肯定了ESD保护电路的良好设计原则,而且指出了脉冲上升时间在确定故障位置方面的重要性。在ESD模拟器规范中允许较宽的上升时间范围(例如MIL-STD Method 3015.6 Notice 7中的0- 10ns范围和EOS/ESD协会HBM标准中的2- 10ns范围),可能会导致在允许范围内不同上升时间的ESD脉冲将能量沉积到设备的不同位置,并产生不相关的ESD阈值。
{"title":"Thermal breakdown of VLSI by ESD pulses","authors":"D. Lin","doi":"10.1109/RELPHY.1990.66101","DOIUrl":"https://doi.org/10.1109/RELPHY.1990.66101","url":null,"abstract":"A three-dimensional thermal model to determine the temperature rise and voltage build-up of VLSI devices stressed by human-body model (HBM) electrostatic discharges (ESD) is discussed. Application of the model to a specific device is yields failure thresholds and failure sites in agreement with the experimental results. This detailed model can be used to evaluate and improve designs of ESD protection circuits. It not only reconfirms the good design principles for ESD protection circuits, but also points out the importance of pulse risetime in determining the failure site. Allowing a wide range in risetime in ESD simulator specifications (such as the 0-10 ns range in MIL-STD Method 3015.6 Notice 7 and the 2-10 ns range in the EOS/ESD Association HBM Standard), may cause ESD pulses of different risetimes within the allowable range to deposit energy to different spots in a device and yield uncorrelatable ESD thresholds.<<ETX>>","PeriodicalId":409540,"journal":{"name":"28th Annual Proceedings on Reliability Physics Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122932558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Building reliability into EPROMs 在eprom中构建可靠性
Pub Date : 1990-03-27 DOI: 10.1109/RELPHY.1990.66053
D. Baglee, Lynn Nannemann, C. Huang
Four areas for achieving a stable, reliable process in a high volume environment are considered: (a) process capability in a manufacturing environment; (b) manufacturing control; (c) assessment of process interactions; (d) process monitoring. These areas are discussed, and suggestions for their application are made.<>
考虑了在大批量环境中实现稳定、可靠工艺的四个方面:(a)制造环境中的工艺能力;(b)生产控制;(c)过程相互作用的评价;(d)过程监测。对这些方面进行了讨论,并对其应用提出了建议。
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引用次数: 16
期刊
28th Annual Proceedings on Reliability Physics Symposium
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