Thermal breakdown of VLSI by ESD pulses

Abstract

A three-dimensional thermal model to determine the temperature rise and voltage build-up of VLSI devices stressed by human-body model (HBM) electrostatic discharges (ESD) is discussed. Application of the model to a specific device is yields failure thresholds and failure sites in agreement with the experimental results. This detailed model can be used to evaluate and improve designs of ESD protection circuits. It not only reconfirms the good design principles for ESD protection circuits, but also points out the importance of pulse risetime in determining the failure site. Allowing a wide range in risetime in ESD simulator specifications (such as the 0-10 ns range in MIL-STD Method 3015.6 Notice 7 and the 2-10 ns range in the EOS/ESD Association HBM Standard), may cause ESD pulses of different risetimes within the allowable range to deposit energy to different spots in a device and yield uncorrelatable ESD thresholds.<>