Prototyping and testing of analog integrated circuits

Abstract

The author describes various procedures to minimize risks involved in prototyping of analogue and mixed signal integrated circuits at external fabs and compares different approaches of minimizing NRE costs. Additionally the author describes Multi Product Wafer (MPW) or Multi Layer Mask (MLM) service and procedures of parallel processing of different design versions on one mask set. Furthermore he gives some guidelines for efficient production ramp-up and yield optimization and opens a discussion on the optimization on back-end assembly and test activities. Finally several online tools provided by foundries from the engineering phase through production will be discussed.