Pub Date : 2009-11-17DOI: 10.1109/EPEPS.2009.5338441
Y. H. Tau, M. Chan
This paper illustrates many different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topic to discuss in this paper and certainly impedance (Z) profile and transient analysis will be performed to observe the noise frequency and accurately address the root cause. All the above will be verified through comprehensive validation data.
{"title":"Next generation I/O power delivery design through SIPD co-analysis & comprehensive platform validation","authors":"Y. H. Tau, M. Chan","doi":"10.1109/EPEPS.2009.5338441","DOIUrl":"https://doi.org/10.1109/EPEPS.2009.5338441","url":null,"abstract":"This paper illustrates many different approaches in solving I/O power delivery noise issues and walk through pre-silicon design solution. It covers circuit and architectural design influence, on silicon and on board decoupling solutions selection and package and platform design optimization. SIPD co-simulations and appropriate package return path are the main topic to discuss in this paper and certainly impedance (Z) profile and transient analysis will be performed to observe the noise frequency and accurately address the root cause. All the above will be verified through comprehensive validation data.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121264179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206286
F. Khalek, H. Mostafa, M. Anis
Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to become worse especially for sub-90-nm technology nodes. In this paper, an analytical model for the phase noise variability in ring oscillators is proposed. The proposed model has been verified using Monte Carlo SPICE simulations for an industrial 65-nm CMOS technology and is found in good agreement. The model shows that for the commonly used differential-pair-based ring oscillators, the main contribution in phase noise variability comes from the differential pair tail transistor. It also shows that the phase noise variability is reduced as the supply voltage increases. These results can be used to mitigate the phase noise variability and improve the yield through proper sizing of the tail transistor or higher supply voltage.
{"title":"Statistical model for ring oscillator phase noise variability accounting for within-die process variation","authors":"F. Khalek, H. Mostafa, M. Anis","doi":"10.1109/ASQED.2009.5206286","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206286","url":null,"abstract":"Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to become worse especially for sub-90-nm technology nodes. In this paper, an analytical model for the phase noise variability in ring oscillators is proposed. The proposed model has been verified using Monte Carlo SPICE simulations for an industrial 65-nm CMOS technology and is found in good agreement. The model shows that for the commonly used differential-pair-based ring oscillators, the main contribution in phase noise variability comes from the differential pair tail transistor. It also shows that the phase noise variability is reduced as the supply voltage increases. These results can be used to mitigate the phase noise variability and improve the yield through proper sizing of the tail transistor or higher supply voltage.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117202208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206294
D. Deschacht, Y. Quéré
Constant evolution in integrated circuit technology has led to an increase in digital chip switching speed. There is thus growing interest in inductance associated with signal lines. In this study, for a three coupled-line distributed system, it is demonstrated that crosstalk voltages observed at their termination result from output modal voltage combinations generated when a mode propagates under particular input configurations. Crosstalk voltages were also found to be equal to the additivity of the electric and magnetic effects, both taken independently. Those demonstrations are realized because of a decoupling technique allowing the coupled-line system description as only an isolated line system. This decoupled system propagates the considered mode and depends on effective electrical parameters.
{"title":"Capacitive and inductive couplings in a distributed RLC interconnection line system: Additivity waveforms","authors":"D. Deschacht, Y. Quéré","doi":"10.1109/ASQED.2009.5206294","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206294","url":null,"abstract":"Constant evolution in integrated circuit technology has led to an increase in digital chip switching speed. There is thus growing interest in inductance associated with signal lines. In this study, for a three coupled-line distributed system, it is demonstrated that crosstalk voltages observed at their termination result from output modal voltage combinations generated when a mode propagates under particular input configurations. Crosstalk voltages were also found to be equal to the additivity of the electric and magnetic effects, both taken independently. Those demonstrations are realized because of a decoupling technique allowing the coupled-line system description as only an isolated line system. This decoupled system propagates the considered mode and depends on effective electrical parameters.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123581579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206241
Jenn-Tzer Yang, De-Wei Shen, P. Tsai, Ming-Jeui Wu
In this paper, a 2.4GHz radio frequency (RF) CMOS receiver based on all active devices for Bluetooth applications is presented. In this receiver, it is integrated with a low noise amplifier (LNA), a mixer, and a voltage controlled oscillator (VCO). The LNA design is used a differential output configure and high-Q active inductors to obtain low noise figure (NF) and high enough power gain. In the mixer design, a high linearity topology and low power consumption are designed. The VCO circuit based on high-Q active inductors and cross-coupled architecture is applied. The integration of the LNA, the mixer, and the VCO construct all active devices Bluetooth receive. Using TSMC 0.18um process, the receiver can be operated in 2.4GHz frequency for Bluetooth applications. Simulation results show that the receiver have the conversion gain of 16.2dB, the sensitivity of −101.5dBm, the noise figure of 2.5dB, the 1dB compression of −26.5dBm, and the IIP3 of −19.7dBm, respectively. The power consumption of the proposed receiver is about 42mW at 1.8V power supply.
{"title":"A CMOS radio frequency receiver for Bluetooth applications","authors":"Jenn-Tzer Yang, De-Wei Shen, P. Tsai, Ming-Jeui Wu","doi":"10.1109/ASQED.2009.5206241","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206241","url":null,"abstract":"In this paper, a 2.4GHz radio frequency (RF) CMOS receiver based on all active devices for Bluetooth applications is presented. In this receiver, it is integrated with a low noise amplifier (LNA), a mixer, and a voltage controlled oscillator (VCO). The LNA design is used a differential output configure and high-Q active inductors to obtain low noise figure (NF) and high enough power gain. In the mixer design, a high linearity topology and low power consumption are designed. The VCO circuit based on high-Q active inductors and cross-coupled architecture is applied. The integration of the LNA, the mixer, and the VCO construct all active devices Bluetooth receive. Using TSMC 0.18um process, the receiver can be operated in 2.4GHz frequency for Bluetooth applications. Simulation results show that the receiver have the conversion gain of 16.2dB, the sensitivity of −101.5dBm, the noise figure of 2.5dB, the 1dB compression of −26.5dBm, and the IIP3 of −19.7dBm, respectively. The power consumption of the proposed receiver is about 42mW at 1.8V power supply.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206285
Lining Zhang, Jian Zhang, Feng Liu, Lin Chen, Yiwen Xu, Wang Zhou, F. He
In this paper an analytic channel potential-based model is proposed to predict the dynamic depletion behavior of surrounding-gate (SRG) MOSFETs with arbitrary doping level. The key input voltage equation is derived out by solving Poisson's equation approximately with arbitrary doping in the cylindrical coordinate. Combined with the surface-centric potential relationship, the electrostatic potential solution along the radius of both intrinsic and heavily doped SRG is obtained. With the potential solutions at the source and drain sides of the channel, the analytic drain current model is provided to calculate the current characteristics of the SRG MOSFET. The presented model can realize transition from partial depletion to full depletion of SRG MOSFET, which is validated by numerical simulation.
{"title":"An analytic channel potential based model for dynamic depletion surrounding-gate mosfets with arbitrary doping level","authors":"Lining Zhang, Jian Zhang, Feng Liu, Lin Chen, Yiwen Xu, Wang Zhou, F. He","doi":"10.1109/ASQED.2009.5206285","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206285","url":null,"abstract":"In this paper an analytic channel potential-based model is proposed to predict the dynamic depletion behavior of surrounding-gate (SRG) MOSFETs with arbitrary doping level. The key input voltage equation is derived out by solving Poisson's equation approximately with arbitrary doping in the cylindrical coordinate. Combined with the surface-centric potential relationship, the electrostatic potential solution along the radius of both intrinsic and heavily doped SRG is obtained. With the potential solutions at the source and drain sides of the channel, the analytic drain current model is provided to calculate the current characteristics of the SRG MOSFET. The presented model can realize transition from partial depletion to full depletion of SRG MOSFET, which is validated by numerical simulation.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206288
H. Mostafa, M. Anis, M. Elmasry
Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.
{"title":"Comparative analysis of process variation impact on flip-flops soft error rate","authors":"H. Mostafa, M. Anis, M. Elmasry","doi":"10.1109/ASQED.2009.5206288","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206288","url":null,"abstract":"Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130625256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206271
Nurqamarina Binti Mohd Noor, A. Saparon, Yusrina Yusof, Mahmud Adnan
As the memory enters submicron technology, new test algorithms that are able to give a better fault coverage such as to detect single-cell fault and all intra-word coupling fault (CF) have been widely developed. In order to implement this algorithm to the memory, test techniques such as BIST are utilized. Common types of programmable memory built-in-self tests (PMBIST) are microcode-based PMBIST and FSM-based PMBIST. The popular approaches of designing various kinds of PMBIST architectures are either by targeting to reach specific testing requirement such as full speed and at speed or by considering the cost-constraint and area overhead for low-cost or low-area design. In this paper, FSM-based BIST is designed to enable detecting both single-cell dynamic fault such as read destructive fault (RDF), deceptive read destructive fault (DRDF), and all intra-word coupling faults (CF) in a synchronous SRAM under low-area constraint of test requirement.
{"title":"Area-effective programmable FSM-based MBIST for synchronous SRAM","authors":"Nurqamarina Binti Mohd Noor, A. Saparon, Yusrina Yusof, Mahmud Adnan","doi":"10.1109/ASQED.2009.5206271","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206271","url":null,"abstract":"As the memory enters submicron technology, new test algorithms that are able to give a better fault coverage such as to detect single-cell fault and all intra-word coupling fault (CF) have been widely developed. In order to implement this algorithm to the memory, test techniques such as BIST are utilized. Common types of programmable memory built-in-self tests (PMBIST) are microcode-based PMBIST and FSM-based PMBIST. The popular approaches of designing various kinds of PMBIST architectures are either by targeting to reach specific testing requirement such as full speed and at speed or by considering the cost-constraint and area overhead for low-cost or low-area design. In this paper, FSM-based BIST is designed to enable detecting both single-cell dynamic fault such as read destructive fault (RDF), deceptive read destructive fault (DRDF), and all intra-word coupling faults (CF) in a synchronous SRAM under low-area constraint of test requirement.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206302
Nayereh Ghobadi, A. Afzali-Kusha, E. Asl-Soleimani
In this paper, an analytical model for the HCI induced trap generation in the gate oxide and the degradation of a triple gate bulk FinFET is presented. The model which is obtained by solving the Reaction-Diffusion equations multi-dimensionally, includes the geometry dependence of the time-exponent of HCI degradation of the structure. In this framework, the electric field distribution and the maximum lateral electric field near the drain region are obtained through solving the Poisson's equation in the saturation region near the drain. Also, the nth power law MOS model is used to model the saturation current and its degradation. The accuracy of the HCI model is verified using experimental results.
{"title":"Analytical modeling of Hot Carrier Injection induced degradation in triple gate bulk FinFETs","authors":"Nayereh Ghobadi, A. Afzali-Kusha, E. Asl-Soleimani","doi":"10.1109/ASQED.2009.5206302","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206302","url":null,"abstract":"In this paper, an analytical model for the HCI induced trap generation in the gate oxide and the degradation of a triple gate bulk FinFET is presented. The model which is obtained by solving the Reaction-Diffusion equations multi-dimensionally, includes the geometry dependence of the time-exponent of HCI degradation of the structure. In this framework, the electric field distribution and the maximum lateral electric field near the drain region are obtained through solving the Poisson's equation in the saturation region near the drain. Also, the nth power law MOS model is used to model the saturation current and its degradation. The accuracy of the HCI model is verified using experimental results.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121557509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206272
V. Narang, B. Arya, K. Rajagopal
As technology is shrinking to sub 100nm, the sensitivity of circuits towards Process, Temperature, Voltage (PTV) and load variations is limiting circuit performance and yield [1–3]. For example in the specific case of IOs, it is difficult to meet various specifications like the rise and fall times, current drive strength, jitter, power and ground bounce across the wide range of I/O operating condition. Driver circuits are oversized to meet performance goals at slow corners. However, this leads to high current and Simultaneous Switching Noise (SSN) at fast corners. [1]. Further, high output edge switching rates lead to EMI issues [4]. In this paper, we propose a technique which can address the EMI and noise concerns without compromising the I/O performance. Our results show that the proposed scheme offers advantage over various PTV compensation schemes which do not target load compensation. The proposed scheme also offers advantage over the traditional slew rate control schemes which target PTV as well as load compensation but require a performance - noise tradeoff.
{"title":"Novel low delay slew rate control I/Os","authors":"V. Narang, B. Arya, K. Rajagopal","doi":"10.1109/ASQED.2009.5206272","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206272","url":null,"abstract":"As technology is shrinking to sub 100nm, the sensitivity of circuits towards Process, Temperature, Voltage (PTV) and load variations is limiting circuit performance and yield [1–3]. For example in the specific case of IOs, it is difficult to meet various specifications like the rise and fall times, current drive strength, jitter, power and ground bounce across the wide range of I/O operating condition. Driver circuits are oversized to meet performance goals at slow corners. However, this leads to high current and Simultaneous Switching Noise (SSN) at fast corners. [1]. Further, high output edge switching rates lead to EMI issues [4]. In this paper, we propose a technique which can address the EMI and noise concerns without compromising the I/O performance. Our results show that the proposed scheme offers advantage over various PTV compensation schemes which do not target load compensation. The proposed scheme also offers advantage over the traditional slew rate control schemes which target PTV as well as load compensation but require a performance - noise tradeoff.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128170492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206395
Mahsa Tahermaram, M. Vadizadeh, Hamdam Ghanatian, M. Fathipour
In this paper, we introduce a novel double gate SHOT which provides at least the drain current twice higher than that of the conventional single gate SHOT structure. Improved characteristics are originated from the high velocity electron injection at the source edge due to the band offset energy. However, these devices suffer from large off-state current. The analysis of the off-state current characteristics shows that provided 90% reduction in off-stat current. Based on this analysis, we proposed use of work function engineering as well as asymmetric gate oxide at the overlapped region to minimize the magnitude of GIDL current which is the main component of the off-state current.
{"title":"Novel techniques for off-state current components reduction in double gate source-heterojunction-MOS-transistor","authors":"Mahsa Tahermaram, M. Vadizadeh, Hamdam Ghanatian, M. Fathipour","doi":"10.1109/ASQED.2009.5206395","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206395","url":null,"abstract":"In this paper, we introduce a novel double gate SHOT which provides at least the drain current twice higher than that of the conventional single gate SHOT structure. Improved characteristics are originated from the high velocity electron injection at the source edge due to the band offset energy. However, these devices suffer from large off-state current. The analysis of the off-state current characteristics shows that provided 90% reduction in off-stat current. Based on this analysis, we proposed use of work function engineering as well as asymmetric gate oxide at the overlapped region to minimize the magnitude of GIDL current which is the main component of the off-state current.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115893408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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