D. Ji, C. Gupta, Silvia H. Chan, Anchal Agarwal, Wenwen Li, S. Keller, U. Mishra, S. Chowdhury
{"title":"Demonstrating >1.4 kV OG-FET performance with a novel double field-plated geometry and the successful scaling of large-area devices","authors":"D. Ji, C. Gupta, Silvia H. Chan, Anchal Agarwal, Wenwen Li, S. Keller, U. Mishra, S. Chowdhury","doi":"10.1109/IEDM.2017.8268359","DOIUrl":null,"url":null,"abstract":"A normally off (V<inf>th</inf> = 4.7 V) vertical GaN OG-FET with a 10 nm UID-GaN channel interlayer and a 50 nm in-situ Al<inf>2</inf>O<inf>3</inf> gate dielectric has been successfully demonstrated and scaled for higher current operation. By using a novel double field-plated structure for mitigating peak electric field, a high off-state breakdown voltage over 1.4 kV was achieved with a low specific on-state resistance (RON, SP) of 2.2 mΩ.cm<sup>2</sup>. The MOCVD regrown 10 nm GaN channel interlayer enabled a channel resistance lower than 10 Qmm and an average channel electron mobility of 185 cm<sup>2</sup>/Vs. The fabricated large-area transistor with a total area of 400 μm × 500 μm offered a breakdown voltage of 900 V and an on-state resistance (R<inf>on</inf>) of 4.1 Q. Results indicate the potential of vertical GaN OG-FETs for over kV range of power electronics applications.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"50","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268359","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 50
Abstract
A normally off (Vth = 4.7 V) vertical GaN OG-FET with a 10 nm UID-GaN channel interlayer and a 50 nm in-situ Al2O3 gate dielectric has been successfully demonstrated and scaled for higher current operation. By using a novel double field-plated structure for mitigating peak electric field, a high off-state breakdown voltage over 1.4 kV was achieved with a low specific on-state resistance (RON, SP) of 2.2 mΩ.cm2. The MOCVD regrown 10 nm GaN channel interlayer enabled a channel resistance lower than 10 Qmm and an average channel electron mobility of 185 cm2/Vs. The fabricated large-area transistor with a total area of 400 μm × 500 μm offered a breakdown voltage of 900 V and an on-state resistance (Ron) of 4.1 Q. Results indicate the potential of vertical GaN OG-FETs for over kV range of power electronics applications.