{"title":"Impact of high-k dielectrics and spacer layers on the elctrical performance of symmetrical double gate MOSFETs","authors":"S. Bhattacherjee, A. Biswas","doi":"10.1109/ELECTRO.2009.5441178","DOIUrl":null,"url":null,"abstract":"In this paper, analytical models for threshold voltage Vt and subthreshold slope S for symmetric double gate MOSFETs with high-k dielectrics are proposed. Analytical approaches for predicting Vt and S are developed by considering effects of fringing electric field, interface trap charge density and sidewall spacers. The proposed model has been employed to calculate Vt, S and drain induced barrier lowering (DIBL) of DG MOSFETs with different gate dielectrics for various values of effective oxide thickness (EOT). Also the effect of sidewall spacers on Vt has been predicted. Accuracy of models has been verified by comparing analytical results obtained from proposed models with the reported simulated data.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTRO.2009.5441178","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, analytical models for threshold voltage Vt and subthreshold slope S for symmetric double gate MOSFETs with high-k dielectrics are proposed. Analytical approaches for predicting Vt and S are developed by considering effects of fringing electric field, interface trap charge density and sidewall spacers. The proposed model has been employed to calculate Vt, S and drain induced barrier lowering (DIBL) of DG MOSFETs with different gate dielectrics for various values of effective oxide thickness (EOT). Also the effect of sidewall spacers on Vt has been predicted. Accuracy of models has been verified by comparing analytical results obtained from proposed models with the reported simulated data.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
