Internal power modelling and minimization in CMOS inverters

Abstract

We present in this paper an alternative for the internal (short-circuit and overshoot) power dissipation estimation of CMOS structures. Using a first order macro-modelling, we consider submicronic additional effects such as: input slow dependency of short-circuit currents and input-to-output coupling. Considering an equivalent capacitance concept we directly compare the different power components. Validations are presented by comparing simulated values (HSPICE level 6, foundry model 0.7 /spl mu/m) to calculated ones. Application to buffer design enlightens the importance of the internal power component and clearly shows that common sizing alternatives for power and delay minimization can be considered.