Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582433
I. Ozimek, R. Verlic, J. Tasic
Summary form only given. Certain real-time applications (e.g. signal filtering and processing in a digital communication system) require the use of a special massively parallel computing structure, called the systolic array structure, to achieve acceptable performance. To implement an algorithm this way, we need a mapping procedure to map a set of equations, which describe the algorithm, to the systolic army. This mapping consists of scheduling (i.e. time mapping, mapping of each DG node to a particular time instant) and space mapping (mapping of each DG node to a systolic array cell). In the paper we propose a new approach to scheduling of complicated algorithms (that are described by a set of equations, fulfilling the requirement of regularity i.e. constant dependence vectors). It takes into account the exact computational requirements of the basic arithmetic operations used and yields near optimal scheduling from the viewpoint of execution speed of the resulting implementation.
{"title":"Optimal scheduling for fast systolic array implementations","authors":"I. Ozimek, R. Verlic, J. Tasic","doi":"10.1109/EDTC.1997.582433","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582433","url":null,"abstract":"Summary form only given. Certain real-time applications (e.g. signal filtering and processing in a digital communication system) require the use of a special massively parallel computing structure, called the systolic array structure, to achieve acceptable performance. To implement an algorithm this way, we need a mapping procedure to map a set of equations, which describe the algorithm, to the systolic army. This mapping consists of scheduling (i.e. time mapping, mapping of each DG node to a particular time instant) and space mapping (mapping of each DG node to a systolic array cell). In the paper we propose a new approach to scheduling of complicated algorithms (that are described by a set of equations, fulfilling the requirement of regularity i.e. constant dependence vectors). It takes into account the exact computational requirements of the basic arithmetic operations used and yields near optimal scheduling from the viewpoint of execution speed of the resulting implementation.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"25 1 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115301127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582380
Chih-Tsun Huang, Cheng-Wen Wu
Systolic architectures for inversion in Galois field (GF(2/sup m/)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.
{"title":"High-speed C-testable systolic array design for Galois-field inversion","authors":"Chih-Tsun Huang, Cheng-Wen Wu","doi":"10.1109/EDTC.1997.582380","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582380","url":null,"abstract":"Systolic architectures for inversion in Galois field (GF(2/sup m/)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115728774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582442
M. Svajda, B. Straka, H. Manhaeve
An integrated off-chip I/sub DDQ/ measuring unit (IOCIMU) is described in this paper. The semi-digital current monitor is designed for the use with standard automatic test equipment (ATE). Simulations of the monolithic monitor implemented in a 2-/spl mu/m BiCMOS technology show an accuracy better than 1% for currents in the range from 0 to 1 mA and a test rate up to 10 kHz.
{"title":"A monolithic off-chip IDDQ monitor","authors":"M. Svajda, B. Straka, H. Manhaeve","doi":"10.1109/EDTC.1997.582442","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582442","url":null,"abstract":"An integrated off-chip I/sub DDQ/ measuring unit (IOCIMU) is described in this paper. The semi-digital current monitor is designed for the use with standard automatic test equipment (ATE). Simulations of the monolithic monitor implemented in a 2-/spl mu/m BiCMOS technology show an accuracy better than 1% for currents in the range from 0 to 1 mA and a test rate up to 10 kHz.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582411
Hoon Choi, S. Hwang
We address a way to improve the accuracy of support-set finding method for a probability-based power estimation of combinational circuits. Support-set finding methods to build local BDDs have been proposed to handle large circuits. However because they consider only the shallow reconvergence, they are not accurate enough to be used in the power optimization. To solve this problem, we propose a new algorithm, Feather algorithm, which can efficiently detect minimal support-set with 100% reconvergent node detection rate. The experimental results show that the average error of our proposed method is 0.1% for the total power and 1.6% for the node-specific power.
{"title":"Improving the accuracy of support-set finding method for power estimation of combinational circuits","authors":"Hoon Choi, S. Hwang","doi":"10.1109/EDTC.1997.582411","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582411","url":null,"abstract":"We address a way to improve the accuracy of support-set finding method for a probability-based power estimation of combinational circuits. Support-set finding methods to build local BDDs have been proposed to handle large circuits. However because they consider only the shallow reconvergence, they are not accurate enough to be used in the power optimization. To solve this problem, we propose a new algorithm, Feather algorithm, which can efficiently detect minimal support-set with 100% reconvergent node detection rate. The experimental results show that the average error of our proposed method is 0.1% for the total power and 1.6% for the node-specific power.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117017594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582443
A. Kristof
The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance.
{"title":"Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections","authors":"A. Kristof","doi":"10.1109/EDTC.1997.582443","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582443","url":null,"abstract":"The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128497162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582445
T. Röwekamp, L. Peters
Summary form only given. We present a new smart sensor architecture for visual motion-optical flow-estimation. As the system operates in real-time it is very well suited for collision avoidance on autonomous mobile platforms. The core of the system is an ASIC in standard digital CMOS technology, which forms a pipeline with a feedback path for on-line image processing. The presented implementation was tested on image frames of 128/spl times/128 pixel size.
{"title":"A real-time smart sensor system for visual motion estimation","authors":"T. Röwekamp, L. Peters","doi":"10.1109/EDTC.1997.582445","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582445","url":null,"abstract":"Summary form only given. We present a new smart sensor architecture for visual motion-optical flow-estimation. As the system operates in real-time it is very well suited for collision avoidance on autonomous mobile platforms. The core of the system is an ASIC in standard digital CMOS technology, which forms a pipeline with a feedback path for on-line image processing. The presented implementation was tested on image frames of 128/spl times/128 pixel size.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"202 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114104589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582435
J. Walrath, R. Vemuri, William Bradley
Summary form only given. A performance model for a typical design represented in a high-level description language can be generated by augmenting the design components with attributes and evaluation rules. An attribute represents some performance aspect of a design that can be either assigned a base initial value or calculated using an evaluation rule. Heat dissipation, dynamic power consumption, and maximum throughput rate are just a few examples of various performance aspects that can be represented with attributes. Evaluation rules contained in the performance model can be classified as either equational or procedural. An equational performance model is a model containing only evaluation rules that are composed of mathematical operations such as addition, subtraction, and so forth. Likewise, a procedural performance model may contain equational rules, but it also has rules composed of complex programming constructs such as an assignment statement, if-then-else, case, and while control constructs and procedure calls. Our method for performance verification involves placing relational constraints on attributes in the performance model and determining whether all constraints can be satisfied simultaneously. Interval mathematics provides a convenient technique to represent relational constraints as intervals. Each attribute has an initial interval from negative infinity to positive infinity. Further constraints are specified by the user, the interval analysis technique is applied, and a verification result is produced.
{"title":"Performance verification using partial evaluation and interval analysis","authors":"J. Walrath, R. Vemuri, William Bradley","doi":"10.1109/EDTC.1997.582435","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582435","url":null,"abstract":"Summary form only given. A performance model for a typical design represented in a high-level description language can be generated by augmenting the design components with attributes and evaluation rules. An attribute represents some performance aspect of a design that can be either assigned a base initial value or calculated using an evaluation rule. Heat dissipation, dynamic power consumption, and maximum throughput rate are just a few examples of various performance aspects that can be represented with attributes. Evaluation rules contained in the performance model can be classified as either equational or procedural. An equational performance model is a model containing only evaluation rules that are composed of mathematical operations such as addition, subtraction, and so forth. Likewise, a procedural performance model may contain equational rules, but it also has rules composed of complex programming constructs such as an assignment statement, if-then-else, case, and while control constructs and procedure calls. Our method for performance verification involves placing relational constraints on attributes in the performance model and determining whether all constraints can be satisfied simultaneously. Interval mathematics provides a convenient technique to represent relational constraints as intervals. Each attribute has an initial interval from negative infinity to positive infinity. Further constraints are specified by the user, the interval analysis technique is applied, and a verification result is produced.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121677219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582387
L. T. Walczowski, D. Nalbantis, W. Waller, K. Shi
A World Wide Web (WWW) based client/server system has been developed which allows server-side process independent layout generators to generate the design rule correct geometry of analogue components such as resistors, capacitors and transistors for a design system running on a local workstation. The complete system is based on the bidirectional interface between a WWW browser and a VLSI design system, with layout generators running remotely on a WWW server.
{"title":"Analogue layout generation by World Wide Web server-based agents","authors":"L. T. Walczowski, D. Nalbantis, W. Waller, K. Shi","doi":"10.1109/EDTC.1997.582387","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582387","url":null,"abstract":"A World Wide Web (WWW) based client/server system has been developed which allows server-side process independent layout generators to generate the design rule correct geometry of analogue components such as resistors, capacitors and transistors for a design system running on a local workstation. The complete system is based on the bidirectional interface between a WWW browser and a VLSI design system, with layout generators running remotely on a WWW server.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127667954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582370
M. Sachdev
The effectiveness of I/sub DDQ/ testing in deep sub-micron is threatened by the increased transistor sub-threshold leakage current. In this article, we survey possible solutions and propose a deep sub-micron I/sub DDQ/ test mode. The methodology provides means for unambiguous measurements of I/sub DDQ/ components and defect diagnosis. The effectiveness of the test mode is demonstrated with a real life example.
{"title":"Deep sub-micron I/sub DDQ/ testing: issues and solutions","authors":"M. Sachdev","doi":"10.1109/EDTC.1997.582370","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582370","url":null,"abstract":"The effectiveness of I/sub DDQ/ testing in deep sub-micron is threatened by the increased transistor sub-threshold leakage current. In this article, we survey possible solutions and propose a deep sub-micron I/sub DDQ/ test mode. The methodology provides means for unambiguous measurements of I/sub DDQ/ components and defect diagnosis. The effectiveness of the test mode is demonstrated with a real life example.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126461947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582409
L. Benini, G. Micheli, E. Macii, M. Poncino, R. Scarsi
Recent results have shown that clock-gating techniques are effective in reducing the total power consumption of sequential circuits. Unfortunately, such techniques assume the availability of the state transition graph of the target system, and rely on explicit algorithms whose complexity is polynomial in the number of states, that is, exponential in the number of state variables. This assumption poses serious limitations on the size of the circuits for which automatic gated-clock generation is feasible. In this paper we propose fully symbolic algorithms for the automatic extraction and synthesis of the clock-gating circuitry for large control-oriented sequential designs. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to extend the applicability of gated-clock architectures to designs implemented by synchronous networks. As a result, we can deal with circuits for which the explicit state transition graph is too large to be generated and/or manipulated. Moreover, symbolic manipulation techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 36% have been obtained on controllers containing up to 21 registers.
{"title":"Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks","authors":"L. Benini, G. Micheli, E. Macii, M. Poncino, R. Scarsi","doi":"10.1109/EDTC.1997.582409","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582409","url":null,"abstract":"Recent results have shown that clock-gating techniques are effective in reducing the total power consumption of sequential circuits. Unfortunately, such techniques assume the availability of the state transition graph of the target system, and rely on explicit algorithms whose complexity is polynomial in the number of states, that is, exponential in the number of state variables. This assumption poses serious limitations on the size of the circuits for which automatic gated-clock generation is feasible. In this paper we propose fully symbolic algorithms for the automatic extraction and synthesis of the clock-gating circuitry for large control-oriented sequential designs. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to extend the applicability of gated-clock architectures to designs implemented by synchronous networks. As a result, we can deal with circuits for which the explicit state transition graph is too large to be generated and/or manipulated. Moreover, symbolic manipulation techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 36% have been obtained on controllers containing up to 21 registers.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130086665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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