{"title":"A 84.7-DR wide BW incremental ADC using CT structure","authors":"Ting-Yang Wang, Tai-Cheng Lee","doi":"10.1109/VLSI-DAT.2015.7114519","DOIUrl":null,"url":null,"abstract":"This work uses continuous-tome (CT) structure to make the sigma-delta modulator faster and consuming less power. A third-order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the paper. The modulator is operated at 100MHz sampling clock. It achieves dynamic range of 84.7 dB, peak SNDR of 73.82 dB within the 737-kHz bandwidth. This chip dissipates 6.6mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114519","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work uses continuous-tome (CT) structure to make the sigma-delta modulator faster and consuming less power. A third-order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the paper. The modulator is operated at 100MHz sampling clock. It achieves dynamic range of 84.7 dB, peak SNDR of 73.82 dB within the 737-kHz bandwidth. This chip dissipates 6.6mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.
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