Improved unified interconnect unit for high speed and scalable FPGA

Lei Li, Jian Wang, Jinmei Lai
{"title":"Improved unified interconnect unit for high speed and scalable FPGA","authors":"Lei Li, Jian Wang, Jinmei Lai","doi":"10.1109/ASICON.2013.6811912","DOIUrl":null,"url":null,"abstract":"This paper presents a completely unified interconnect unit (UINT) including unified input and output multiplexers (UIM and UOM) which are usually non-repeatable [1-3]. UINT ensures different logic modules could have exactly the identical interconnect circuit, providing higher scalability for FPGAs. Furthermore, Multi-Vt switch circuit combining low threshold voltage and high threshold voltage transistors is put forward to minimize the adverse effects brought by threshold voltage loss and decrease of Supply Voltage in Nanometer technology, attaining high speed performance of FPGA. The proposed interconnect unit is applied to own-designed Fudan Programmable (FDP5) FPGA and realized through 65 nm technology. Post-layout simulation results indicate that the proposed interconnect circuit is well-designed with up to 40% improvement of speed performance compared to the prior work [3] equivalent to the same technology, yet maintaining lower power consumption and smaller area, reduced by 12% and 35% respectively.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"203 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 10th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2013.6811912","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

This paper presents a completely unified interconnect unit (UINT) including unified input and output multiplexers (UIM and UOM) which are usually non-repeatable [1-3]. UINT ensures different logic modules could have exactly the identical interconnect circuit, providing higher scalability for FPGAs. Furthermore, Multi-Vt switch circuit combining low threshold voltage and high threshold voltage transistors is put forward to minimize the adverse effects brought by threshold voltage loss and decrease of Supply Voltage in Nanometer technology, attaining high speed performance of FPGA. The proposed interconnect unit is applied to own-designed Fudan Programmable (FDP5) FPGA and realized through 65 nm technology. Post-layout simulation results indicate that the proposed interconnect circuit is well-designed with up to 40% improvement of speed performance compared to the prior work [3] equivalent to the same technology, yet maintaining lower power consumption and smaller area, reduced by 12% and 35% respectively.
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改进的高速可扩展FPGA统一互连单元
本文提出了一种完全统一的互连单元(UINT),包括通常不可重复的统一输入和输出复用器(UIM和UOM)[1-3]。UINT确保不同的逻辑模块可以具有完全相同的互连电路,为fpga提供更高的可扩展性。此外,为了最大限度地减少纳米技术中阈值电压损失和电源电压降低带来的不利影响,提出了结合低阈值电压和高阈值电压晶体管的Multi-Vt开关电路,实现了FPGA的高速性能。该互连单元采用自主设计的复旦可编程FPGA (FDP5),采用65nm工艺实现。布局后仿真结果表明,所提出的互连电路设计良好,与同等技术的先前工作[3]相比,速度性能提高了40%,同时保持更低的功耗和更小的面积,分别降低了12%和35%。
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