A new asynchronous pipeline template for power and performance optimization

Abstract

Asynchronous circuits are a promising design style for low-power and high-performance applications, where asynchronous templates have been widely used to automate the design of asynchronous circuits to reduce design efforts such as the implementation of hand-shaking mechanisms. Among the templates, pipeline templates are popular in high-performance systems. This paper presents an asynchronous template that can generate pipelines with low glitch-power consumption under the two-phase bundled-data protocol. Moreover, operations of our pipeline template can be hazard-free by simple techniques. We further analyze the timing constraints of pipelines based on the template, and then introduce two practical extensions of using the template. Compared with the prior work considering glitch-power reduction, pipelines using our proposed template can achieve significantly higher performance, lower power consumption, and less area overhead, with similar glitch-power reduction.