Asynchronous circuits are a promising design style for low-power and high-performance applications, where asynchronous templates have been widely used to automate the design of asynchronous circuits to reduce design efforts such as the implementation of hand-shaking mechanisms. Among the templates, pipeline templates are popular in high-performance systems. This paper presents an asynchronous template that can generate pipelines with low glitch-power consumption under the two-phase bundled-data protocol. Moreover, operations of our pipeline template can be hazard-free by simple techniques. We further analyze the timing constraints of pipelines based on the template, and then introduce two practical extensions of using the template. Compared with the prior work considering glitch-power reduction, pipelines using our proposed template can achieve significantly higher performance, lower power consumption, and less area overhead, with similar glitch-power reduction.
{"title":"A new asynchronous pipeline template for power and performance optimization","authors":"Kuan-Hsien Ho, Yao-Wen Chang","doi":"10.1145/2593069.2593074","DOIUrl":"https://doi.org/10.1145/2593069.2593074","url":null,"abstract":"Asynchronous circuits are a promising design style for low-power and high-performance applications, where asynchronous templates have been widely used to automate the design of asynchronous circuits to reduce design efforts such as the implementation of hand-shaking mechanisms. Among the templates, pipeline templates are popular in high-performance systems. This paper presents an asynchronous template that can generate pipelines with low glitch-power consumption under the two-phase bundled-data protocol. Moreover, operations of our pipeline template can be hazard-free by simple techniques. We further analyze the timing constraints of pipelines based on the template, and then introduce two practical extensions of using the template. Compared with the prior work considering glitch-power reduction, pipelines using our proposed template can achieve significantly higher performance, lower power consumption, and less area overhead, with similar glitch-power reduction.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The smart electric grid in the United States is one of the largest and most complex cyber-physical systems (CPS) in the world and contains considerable uncertainties. Probabilistic optimal power flow (OPF) analysis is required to accomplish the electrical and economic operational goals. In this paper, we propose a novel algorithm to accelerate the computation of probabilistic OPF for large-scale smart grids through network reduction (NR). Cumulant-based method and Gram-Charlier expansion theory are used to efficiently obtain the statistics of system states. We develop a more accurate linear mapping method to compute the unknown cumulants. Our method speeds up the computation by up to 4.57X and can improve around 30% accuracy when Hessian matrix is ill-conditioned compared to the previous approach.
{"title":"ClusRed: Clustering and network reduction based probabilistic optimal power flow analysis for large-scale smart grids","authors":"Yi Liang, Deming Chen","doi":"10.1145/2593069.2593106","DOIUrl":"https://doi.org/10.1145/2593069.2593106","url":null,"abstract":"The smart electric grid in the United States is one of the largest and most complex cyber-physical systems (CPS) in the world and contains considerable uncertainties. Probabilistic optimal power flow (OPF) analysis is required to accomplish the electrical and economic operational goals. In this paper, we propose a novel algorithm to accelerate the computation of probabilistic OPF for large-scale smart grids through network reduction (NR). Cumulant-based method and Gram-Charlier expansion theory are used to efficiently obtain the statistics of system states. We develop a more accurate linear mapping method to compute the unknown cumulants. Our method speeds up the computation by up to 4.57X and can improve around 30% accuracy when Hessian matrix is ill-conditioned compared to the previous approach.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127459066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As soft error is a major reliability issue for nanoscale VLSI, addressing it during high level synthesis can have a significant impact on the overall design quality. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables have nonuniform soft error vulnerabilities, we propose a novel reliability-aware register binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive variable vulnerability analysis at the behavioral level, by considering error propagation and masking in both control and data flow. Then an optimization based on integer linear programming is used to incorporate vulnerabilities into the register binding phase with a selective register protection scheme. The experimental results reveal that the proposed technique can achieve significant soft error mitigation (60% coverage of the total vulnerabilities) with a small portion (20%) of register protection.
{"title":"Reliability-aware register binding for control-flow intensive designs","authors":"Liang Chen, M. Tahoori","doi":"10.1145/2593069.2593200","DOIUrl":"https://doi.org/10.1145/2593069.2593200","url":null,"abstract":"As soft error is a major reliability issue for nanoscale VLSI, addressing it during high level synthesis can have a significant impact on the overall design quality. Motivated by the observation that for behavioral designs, especially control-flow intensive ones, variables have nonuniform soft error vulnerabilities, we propose a novel reliability-aware register binding technique to explore more effective soft error mitigation during high level synthesis. We first perform a comprehensive variable vulnerability analysis at the behavioral level, by considering error propagation and masking in both control and data flow. Then an optimization based on integer linear programming is used to incorporate vulnerabilities into the register binding phase with a selective register protection scheme. The experimental results reveal that the proposed technique can achieve significant soft error mitigation (60% coverage of the total vulnerabilities) with a small portion (20%) of register protection.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125921990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, H. Yi, H. Wong, Hongbo Zhang
Directed Self-Assembly (DSA) is a promising technique for contacts/vias patterning, where groups of contacts/vias are patterned by guiding templates. As the templates are patterned by traditional lithography, their shapes may vary due to the process variations, which will ultimately affect the contacts/vias even for the same type of template. Due to the complexity of the DSA process, rigorous process simulation is unacceptably slow for full chip verification. This paper formulate several critical problems in DSA verification, and proposes a design automation methodology that consists of a data preparation and a model learning stage. We present a novel DSA model with Point Correspondence and Segment Distance features for robust learning. Following the methodology, we propose an effective machine learning (ML) based method for DSA hotspot detection. The results of our initial experiments have already demonstrated the high-efficiency of our ML-based approach with over 85% detection accuracy. Compared to the minutes or even hours of simulation time in rigorous method, the methodology in this paper validates the research potential along this direction.
{"title":"Directed Self-Assembly (DSA) Template Pattern Verification","authors":"Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, H. Yi, H. Wong, Hongbo Zhang","doi":"10.1145/2593069.2593125","DOIUrl":"https://doi.org/10.1145/2593069.2593125","url":null,"abstract":"Directed Self-Assembly (DSA) is a promising technique for contacts/vias patterning, where groups of contacts/vias are patterned by guiding templates. As the templates are patterned by traditional lithography, their shapes may vary due to the process variations, which will ultimately affect the contacts/vias even for the same type of template. Due to the complexity of the DSA process, rigorous process simulation is unacceptably slow for full chip verification. This paper formulate several critical problems in DSA verification, and proposes a design automation methodology that consists of a data preparation and a model learning stage. We present a novel DSA model with Point Correspondence and Segment Distance features for robust learning. Following the methodology, we propose an effective machine learning (ML) based method for DSA hotspot detection. The results of our initial experiments have already demonstrated the high-efficiency of our ML-based approach with over 85% detection accuracy. Compared to the minutes or even hours of simulation time in rigorous method, the methodology in this paper validates the research potential along this direction.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123426841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Leonidas Kosmidis, E. Quiñones, J. Abella, G. Farrall, Franck Wartel, F. Cazorla
Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the timing behaviour of the hardware/software platform: execution times of end-to-end runs have to be independent and identically distributed (i.i.d.). Hardware and software solutions have been deployed to accomplish MBPTA requirements. The latter has achieved the i.i.d. properties running on some commercial off-the-shelf (COTS) processor designs. Unfortunately, software randomisation challenges functional verification needed for certification since it introduces indirections through pointers in the code. In this paper we propose a new approach to software randomisation able to contain its functional verification costs. Our approach performs software randomisation statically, as opposed to current dynamic approaches. We carefully review the requirements of the new approach and prove its feasibility.
{"title":"Containing timing-related certification cost in automotive systems deploying complex hardware","authors":"Leonidas Kosmidis, E. Quiñones, J. Abella, G. Farrall, Franck Wartel, F. Cazorla","doi":"10.1145/2593069.2593112","DOIUrl":"https://doi.org/10.1145/2593069.2593112","url":null,"abstract":"Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the timing behaviour of the hardware/software platform: execution times of end-to-end runs have to be independent and identically distributed (i.i.d.). Hardware and software solutions have been deployed to accomplish MBPTA requirements. The latter has achieved the i.i.d. properties running on some commercial off-the-shelf (COTS) processor designs. Unfortunately, software randomisation challenges functional verification needed for certification since it introduces indirections through pointers in the code. In this paper we propose a new approach to software randomisation able to contain its functional verification costs. Our approach performs software randomisation statically, as opposed to current dynamic approaches. We carefully review the requirements of the new approach and prove its feasibility.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125532397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Foundry identification is essential for many tasks including intellectual property protection, trust, and preventing counterfeiting. In this paper, we introduce statistical techniques for foundry detection, specifically for identifying from which foundry a particular chip originates from. The key idea is to consider the distributions of channel lengths and threshold voltages after employing a variant of SAT that extracts these two metrics. We apply Kolmogorov-Smirnov and other statistical tests for comparing the two empirical distributions. Finally, we study the effects of sample size and measurement error on the correct identification rate and establish an interval of confidence using resubstitution techniques.
{"title":"Techniques for foundry identification","authors":"James Bradley Wendt, F. Koushanfar, M. Potkonjak","doi":"10.1145/2593069.2593228","DOIUrl":"https://doi.org/10.1145/2593069.2593228","url":null,"abstract":"Foundry identification is essential for many tasks including intellectual property protection, trust, and preventing counterfeiting. In this paper, we introduce statistical techniques for foundry detection, specifically for identifying from which foundry a particular chip originates from. The key idea is to consider the distributions of channel lengths and threshold voltages after employing a variant of SAT that extracts these two metrics. We apply Kolmogorov-Smirnov and other statistical tests for comparing the two empirical distributions. Finally, we study the effects of sample size and measurement error on the correct identification rate and establish an interval of confidence using resubstitution techniques.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126741654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we study the power vs. performance tradeoff in block-level monolithic 3D IC designs. Our study shows that we can close the power-performance gap between 2D and a theoretical lower bound by up to 50%. We model the inter-tier performance variations caused by a low temperature manufacturing process on the non-bottom tiers. We also model an alternate manufacturing process, where highly resistive tungsten interconnects are used on the bottom tier to withstand a high temperature process on the non bottom tiers. We propose a variation-aware floorplanning technique that makes our design more tolerant to these variations. We demonstrate that our design methods can help us obtain high quality designs even under inter-tier performance variations.
{"title":"Power-performance study of block-level monolithic 3D-ICs considering inter-tier performance variations","authors":"Shreepad Panth, K. Samadi, Yang Du, S. Lim","doi":"10.1145/2593069.2593188","DOIUrl":"https://doi.org/10.1145/2593069.2593188","url":null,"abstract":"In this paper we study the power vs. performance tradeoff in block-level monolithic 3D IC designs. Our study shows that we can close the power-performance gap between 2D and a theoretical lower bound by up to 50%. We model the inter-tier performance variations caused by a low temperature manufacturing process on the non-bottom tiers. We also model an alternate manufacturing process, where highly resistive tungsten interconnects are used on the bottom tier to withstand a high temperature process on the non bottom tiers. We propose a variation-aware floorplanning technique that makes our design more tolerant to these variations. We demonstrate that our design methods can help us obtain high quality designs even under inter-tier performance variations.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we firstly give an overview of the security perimeter in modern automotive systems and propose then a cost effective solution for authentication of communication data. The proposed solution provides end to end protection, it covers the aspects data content and generation time (freshness) and it can be implemented for different standard communication busses without a bus protocol change. Its low overhead makes it in particular suited for short data messages of real time systems, like messages on bandwidth restricted automotive buses.
{"title":"A secure but still safe and low cost automotive communication technique","authors":"R. Zalman, A. Mayer","doi":"10.1145/2593069.2603850","DOIUrl":"https://doi.org/10.1145/2593069.2603850","url":null,"abstract":"In this paper, we firstly give an overview of the security perimeter in modern automotive systems and propose then a cost effective solution for authentication of communication data. The proposed solution provides end to end protection, it covers the aspects data content and generation time (freshness) and it can be implemented for different standard communication busses without a bus protocol change. Its low overhead makes it in particular suited for short data messages of real time systems, like messages on bandwidth restricted automotive buses.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114405654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, for the first time, we model and extract the parasitic capacitance between TSVs and their surrounding wires in 3D IC. For a fast and accurate full-chip extraction, we propose a pattern-matching-based algorithm that considers the physical dimensions of TSVs and neighboring wires and captures their field interactions. Our extraction method is accurate within 1.9% average error for a full-chip-level design while requiring negligible runtime and memory compared with a field solver. We also observe that TSV-to-wire capacitance has a significant impact on the noise of TSV-based connections and the longest path delay. To reduce TSV-to-wire coupling, we present two full-chip optimization methods, i.e., increasing KOZ and guard ring protection that are shown to be highly effective in noise reduction with minimal overhead.
{"title":"Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling","authors":"Yarui Peng, D. Petranovic, S. Lim","doi":"10.1145/2593069.2593139","DOIUrl":"https://doi.org/10.1145/2593069.2593139","url":null,"abstract":"In this paper, for the first time, we model and extract the parasitic capacitance between TSVs and their surrounding wires in 3D IC. For a fast and accurate full-chip extraction, we propose a pattern-matching-based algorithm that considers the physical dimensions of TSVs and neighboring wires and captures their field interactions. Our extraction method is accurate within 1.9% average error for a full-chip-level design while requiring negligible runtime and memory compared with a field solver. We also observe that TSV-to-wire capacitance has a significant impact on the noise of TSV-based connections and the longest path delay. To reduce TSV-to-wire coupling, we present two full-chip optimization methods, i.e., increasing KOZ and guard ring protection that are shown to be highly effective in noise reduction with minimal overhead.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121860346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optical Proximity Correction (OPC) has been widely adopted for resolution enhancement to achieve nanolithography. However, conventional rule-based and model-based OPCs encounter severe difficulties at advanced technology nodes. Inverse Lithography Technique (ILT) that solves the inverse problem of the imaging system becomes a promising solution for OPC. In this paper, we consider simultaneously 1) the design target optimization under nominal process condition and 2) process window minimization with different process corners, and solve the mask optimization problem based on ILT. The proposed method is tested on 32nm designs released by IBM for the ICCAD 2013 contest. Our optimization is implemented in two modes, MOSAIC_fast and MOSAIC_exact, which outperform the first place winner of the ICCAD 2013 contest by 7% and 11%, respectively.
{"title":"MOSAIC: Mask optimizing solution with process window aware inverse correction","authors":"Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, D. Pan","doi":"10.1145/2593069.2593163","DOIUrl":"https://doi.org/10.1145/2593069.2593163","url":null,"abstract":"Optical Proximity Correction (OPC) has been widely adopted for resolution enhancement to achieve nanolithography. However, conventional rule-based and model-based OPCs encounter severe difficulties at advanced technology nodes. Inverse Lithography Technique (ILT) that solves the inverse problem of the imaging system becomes a promising solution for OPC. In this paper, we consider simultaneously 1) the design target optimization under nominal process condition and 2) process window minimization with different process corners, and solve the mask optimization problem based on ILT. The proposed method is tested on 32nm designs released by IBM for the ICCAD 2013 contest. Our optimization is implemented in two modes, MOSAIC_fast and MOSAIC_exact, which outperform the first place winner of the ICCAD 2013 contest by 7% and 11%, respectively.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"54 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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