{"title":"An adaptive timing-driven layout for high speed VLSI","authors":"S. Sutanthavibul, E. Shragowitz","doi":"10.1109/DAC.1990.114835","DOIUrl":null,"url":null,"abstract":"An adaptive timing-driven VLSI layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed the effectiveness of this approach.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"57","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1990.114835","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 57
Abstract
An adaptive timing-driven VLSI layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed the effectiveness of this approach.<>
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