Design for consecutive transparency of cores in system-on-a-chip

Abstract

This paper presents a design-for-consecutive-transparency method that makes a soft core (RTL description) consecutively transparent using integer linear programming. Consecutive transparency of a core guarantees consecutive propagation of arbitrary test/response sequences from the core inputs to the core outputs with some latency. Therefore, it is possible to apply/observe arbitrary test/response sequences to/from an embedded core consecutively at the speed of the system clock by using interconnects and consecutively transparent cores in an SoC. Experimental results show that the proposed method introduces a lower area overhead compared to the bypass method that adds direct paths from PIs to POs with multiplexers.