On-chip analog output response compaction

Abstract

In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal integrated circuits. The integration function is identified as a powerful analog compression scheme and an analog signature analyzer is proposed. The op amp-based implementation allows one to define single and multiple-input versions. The multiple-input analyzer permits the monitoring of some extra internal nodes in addition to the classical output nodes, or the concurrent control of both voltage and current levels. This ability leads to an improvement of the circuit testability and consequently, the on-chip response evaluation gives a higher fault coverage than the off-chip one.