Fast run-time fault location in dependable FPGA-based applications

Abstract

Run-time fault location in field-programmable gate arrays (FPGAs) is important because the resulting diagnostic information can be used to reconfigure the FPGA to tolerate permanent faults. In order to minimize system downtime and increase availability, a fault location technique with very short diagnostic latency is desired. We present a fast technique for run-time FPGA fault location that can be used for high-availability reconfigurable systems. By integrating FPGA fault tolerance and concurrent error detection (CED) techniques, our approach can achieve significant availability improvement by minimizing the number of reconfigurations required for FPGA fault location and recovery. The area overhead of our approach is studied and illustrated using applications implemented in FPGAs.