Bus-based IP Reusable Verification Platform

Abstract

As the VLSI design scale shrinks, traditional verification methods can not satisfy the verification request, because they do not provide enough ability to check the function correctness and can not ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus based verification platform is presented and the reusable efficience can be improved 80% at least. The focus is to increase the productivity of the verification engineer by providing a framework to reuse verification unit.