Encoding with Repeater Insertion for Minimizing Delay in VLSI Interconnects

Abstract

Interconnects dominate system performance in DSM (deep sub-micron) domain. In shrinking technologies, propagation delay of on-chip interconnects is becoming a major concern. The present work tries to combine encoding with repeater insertion to reduce the propagation delay in VLSI interconnects. A new coding algorithm for minimizing delay has been proposed which eliminates the cross talk classes 4, 5 and 6. In addition to it, an attempt has been made to combine the proposed coding scheme with repeater insertion for further delay minimization. To observe the effect of technology on delay minimization, simulations have been carried out at different technological nodes (180, 130, 90 and 65 nm) for different wire lengths (5,10 mm). Experimental results reveal that there is a significant amount of delay reduction because of this coding technique combined with repeater insertion which appears to perform better than existing techniques in literature