Design Implementation of a Low-Power 16T 1-bit Hybrid Full Adder

Abstract

The demand for low-power and energy-efficient computing devices is rising rapidly. One of the important fundamental components of these devices is an adder. Hence, its power consumption needs to be minimized. A 1-bit hybrid full adder employing transmission gates and complementary metal-oxide semiconductor logic is presented in this paper. It provides full swing outputs and consumes very low power in comparison with other presented designs. The layout design, simulation and performance measurement are done in 180 nm and 90 nm technology nodes. The reduction in total power consumption in 180 nm is found to be about 77% and, 89% in 90 nm. In addition, the power-delay product is reduced by 79% in the case of 180 nm and 87% in 90 nm. Furthermore, the area overhead of the proposed design is also less as compared to existing designs.