N. Herfurth, E. Amini, M. Lisker, Jean-Pierre Seifert, C. Boit
{"title":"A scalable & comprehensive resilience concept against optical & physical IC backside attacks","authors":"N. Herfurth, E. Amini, M. Lisker, Jean-Pierre Seifert, C. Boit","doi":"10.1109/IPFA55383.2022.9915714","DOIUrl":null,"url":null,"abstract":"IC security is not ensured until the chip backside is fully protected. This paper presents a comprehensive and VLSI-compatible protection structure to secure integrated circuits (ICs) against all types of physical and optical attacks targeting the IC via the chip backside. The novel method of protecting the IC structure is provided by outsourcing the protection scheme onto a dedicated protection wafer. This protection wafer is then irreversibly bonded to the IC. This process can be performed at wafer level, realising a VLSI-compatible protection scheme. An example integration based on the new approach is described and discussed in detail.The protection wafer consists of a highly doped silicon substrate forming an optical opaque layer. The protection wafer is irreversibly bonded to the IC and electrically contacted by through silicon vias (TSVs). Integrity of the wafer-stack is verified by an electro-optical process. The protection wafer contains several photon-emitting devices. Several p-n junctions on the circuit side of the protected IC sense the optical signals generated by the photon emitting devices on the protection wafer.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"76 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA55383.2022.9915714","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
IC security is not ensured until the chip backside is fully protected. This paper presents a comprehensive and VLSI-compatible protection structure to secure integrated circuits (ICs) against all types of physical and optical attacks targeting the IC via the chip backside. The novel method of protecting the IC structure is provided by outsourcing the protection scheme onto a dedicated protection wafer. This protection wafer is then irreversibly bonded to the IC. This process can be performed at wafer level, realising a VLSI-compatible protection scheme. An example integration based on the new approach is described and discussed in detail.The protection wafer consists of a highly doped silicon substrate forming an optical opaque layer. The protection wafer is irreversibly bonded to the IC and electrically contacted by through silicon vias (TSVs). Integrity of the wafer-stack is verified by an electro-optical process. The protection wafer contains several photon-emitting devices. Several p-n junctions on the circuit side of the protected IC sense the optical signals generated by the photon emitting devices on the protection wafer.