14nm FinFET Device Boost via 2nd Generation Fins Optimized for High Performance CMOS Applications

Abstract

3D TCAD (Technology Computer Aided Design) process and device simulation is used to show that taller and thinner fins at the 14nm device node enable significant DC and RO performance gains for both nFET and pFET short channel devices through improvement in charge inversion andleakage current control. In particular, simulations identify a maximum in the DC and RO performance as a function of the Fin Ratio, defined as the top fin width (TCD) over the bottom fin width (BCD). At long channel, TCAD simulation demonstrates that mobility degradation observed in nFET hardware devices (but not in pFET devices) is due to the effect of quantum confinement in the fin.