The R2-D2 toolchain — Automated porting of safety-critical applications to FPGAs

Steffen Vaas, M. Reichenbach, Ulrich Margull, D. Fey
{"title":"The R2-D2 toolchain — Automated porting of safety-critical applications to FPGAs","authors":"Steffen Vaas, M. Reichenbach, Ulrich Margull, D. Fey","doi":"10.1109/ReConFig.2016.7857192","DOIUrl":null,"url":null,"abstract":"Safety-critical applications require reliable hardware platforms with deterministic behavior. Concerning the increasing demand for performance, current single core solutions are not sufficient anymore. Classical multi-core processors are designed for a general application case, which provide much performance at the expense of determinism and reliability. In safety-critical applications, all required tasks are already known at development time. They are specified by a system description, like AUTOSAR. Thus, a hardware architecture providing one core for each task and one physical link for each data exchange between different tasks can be derived. However, such a highly application-specific architecture is not available. Latest FPGA technologies provide now enough resources to integrate several soft-core processors in one low-cost chip. Furthermore, the cores and their connections can be arranged flexibly in an FPGA. To bridge the gap between safety-critical applications and FPGAs, this approach provides a toolchain as addition to existing AUTOSAR design tools for automatically generating a specific hardware architecture from metadata of an AUTOSAR description. By reducing the complexity of the hardware platform drastically, a reconfigurable, reliable, deterministic, distributed (R2-D2) hardware architecture can be created. The results show that safety-critical tasks can be executed deterministically on one chip in parallel and multiple applications can be mapped to one low-cost FPGA. Furthermore, the latency of the system could be reduced extensively, so new application areas can be accessed.","PeriodicalId":431909,"journal":{"name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2016.7857192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

Safety-critical applications require reliable hardware platforms with deterministic behavior. Concerning the increasing demand for performance, current single core solutions are not sufficient anymore. Classical multi-core processors are designed for a general application case, which provide much performance at the expense of determinism and reliability. In safety-critical applications, all required tasks are already known at development time. They are specified by a system description, like AUTOSAR. Thus, a hardware architecture providing one core for each task and one physical link for each data exchange between different tasks can be derived. However, such a highly application-specific architecture is not available. Latest FPGA technologies provide now enough resources to integrate several soft-core processors in one low-cost chip. Furthermore, the cores and their connections can be arranged flexibly in an FPGA. To bridge the gap between safety-critical applications and FPGAs, this approach provides a toolchain as addition to existing AUTOSAR design tools for automatically generating a specific hardware architecture from metadata of an AUTOSAR description. By reducing the complexity of the hardware platform drastically, a reconfigurable, reliable, deterministic, distributed (R2-D2) hardware architecture can be created. The results show that safety-critical tasks can be executed deterministically on one chip in parallel and multiple applications can be mapped to one low-cost FPGA. Furthermore, the latency of the system could be reduced extensively, so new application areas can be accessed.
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R2-D2工具链-将安全关键应用程序自动移植到fpga
安全关键型应用程序需要具有确定性行为的可靠硬件平台。对于日益增长的性能需求,目前的单核解决方案已经不能满足需求。经典的多核处理器是为一般的应用场景而设计的,它以牺牲确定性和可靠性为代价提供了大量的性能。在安全关键型应用程序中,所有必需的任务在开发时就已经知道了。它们由系统描述指定,如AUTOSAR。因此,可以推导出为每个任务提供一个核心和为不同任务之间的每个数据交换提供一个物理链路的硬件体系结构。然而,这种高度特定于应用程序的体系结构是不可用的。最新的FPGA技术提供了足够的资源,可以在一个低成本芯片中集成多个软核处理器。此外,内核及其连接可以灵活地安排在FPGA中。为了弥合安全关键应用和fpga之间的差距,这种方法提供了一个工具链,作为现有AUTOSAR设计工具的补充,可以从AUTOSAR描述的元数据自动生成特定的硬件架构。通过大幅降低硬件平台的复杂性,可以创建可重构的、可靠的、确定性的、分布式的(R2-D2)硬件架构。结果表明,安全关键任务可以在一个芯片上确定性地并行执行,多个应用可以映射到一个低成本的FPGA上。此外,系统的延迟可以大大降低,因此可以访问新的应用领域。
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