{"title":"A programmable receiver front-end architecture supporting LTE","authors":"Hoda Abdelsalam, E. Hegazi, H. Mostafa, Y. Ismail","doi":"10.1109/ICM.2014.7071797","DOIUrl":null,"url":null,"abstract":"The desire of having applications covering all service specifications tremendously increases the demand for multi-band multi-standard receivers. A programmable receiver front-end architecture for multi-band multi-standard receivers is proposed. The receiver adopts a down-conversion quadrature band-pass FIR charge sampling mixer programmed via its controlling clocks. A time varying impedance matching network provides further selectivity. The architecture is simulated over three different frequencies spanning two octaves (2G, 1G and 500MHz) targeting LTE specifications. The proposed design achieves conversion gain of 23dB to 28dB, Noise Figure (NF) of 7dB to 9dB, out of band IIP3 of -1.9dBm to -5.6dBm, in band IIP3 of -1.5dBm to -5.7dBm and S11 <;-10 dB. The design is implemented using a 65nm CMOS technology.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 26th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2014.7071797","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The desire of having applications covering all service specifications tremendously increases the demand for multi-band multi-standard receivers. A programmable receiver front-end architecture for multi-band multi-standard receivers is proposed. The receiver adopts a down-conversion quadrature band-pass FIR charge sampling mixer programmed via its controlling clocks. A time varying impedance matching network provides further selectivity. The architecture is simulated over three different frequencies spanning two octaves (2G, 1G and 500MHz) targeting LTE specifications. The proposed design achieves conversion gain of 23dB to 28dB, Noise Figure (NF) of 7dB to 9dB, out of band IIP3 of -1.9dBm to -5.6dBm, in band IIP3 of -1.5dBm to -5.7dBm and S11 <;-10 dB. The design is implemented using a 65nm CMOS technology.