{"title":"High-level design validation using algorithmic debugging","authors":"J. Naganuma, T. Ogura, T. Hoshino","doi":"10.1109/EDTC.1994.326833","DOIUrl":null,"url":null,"abstract":"This paper proposes a new environment for high-level LSI design validation using \"Algorithmic Debugging\" and evaluates its benefits on three significant examples. A design is specified at a high-level using the structured analysis (SA) method and some errors included in SA specifications are efficiently located by answering just a few queries from the debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. This environment promises to be an important step towards efficient high-level LSI design validation.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2676 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326833","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper proposes a new environment for high-level LSI design validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples. A design is specified at a high-level using the structured analysis (SA) method and some errors included in SA specifications are efficiently located by answering just a few queries from the debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. This environment promises to be an important step towards efficient high-level LSI design validation.<>
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