Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326896
Rob van Dongen, Vincent Rikkink
High performance analog circuits have been realised on a purely digital Sea-of-Gates Array: an 8 bit weighted current DA-converter (typical INL of 0.2 LSB) and a class AB Opamp that has a quiescent supply current of only 23 /spl mu/A, and that can drive 3.4 V/sub pp/ into a 1 k/spl Omega/ load with a THD<0.1% (5 V supply). Dedicated CAD tools have been developed for a fast and reliable layout of the analog circuitry on the SOG array.<>
{"title":"Advanced analog circuit design on a digital Sea-of-Gates Array","authors":"Rob van Dongen, Vincent Rikkink","doi":"10.1109/EDTC.1994.326896","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326896","url":null,"abstract":"High performance analog circuits have been realised on a purely digital Sea-of-Gates Array: an 8 bit weighted current DA-converter (typical INL of 0.2 LSB) and a class AB Opamp that has a quiescent supply current of only 23 /spl mu/A, and that can drive 3.4 V/sub pp/ into a 1 k/spl Omega/ load with a THD<0.1% (5 V supply). Dedicated CAD tools have been developed for a fast and reliable layout of the analog circuitry on the SOG array.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122445491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326865
S. Bhatia, N. Jha
Previous research in the area of behavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance. We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical testability. A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault effects from module outputs to system outputs. Genesis provided 100% system-level testability for all the synthesized benchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an efficient gate-level sequential test generator. The area overhead of circuits synthesized by Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard testability. Genesis can also easily handle loop constructs in the behavioral specification.<>
{"title":"Genesis: a behavioral synthesis system for hierarchical testability","authors":"S. Bhatia, N. Jha","doi":"10.1109/EDTC.1994.326865","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326865","url":null,"abstract":"Previous research in the area of behavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance. We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical testability. A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault effects from module outputs to system outputs. Genesis provided 100% system-level testability for all the synthesized benchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an efficient gate-level sequential test generator. The area overhead of circuits synthesized by Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard testability. Genesis can also easily handle loop constructs in the behavioral specification.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114148756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326801
Wen Ching Wu, Chung-Len Lee, Jwu-E Chen, Won Yih Lin
The authors target the pattern partitioning on the distributed fault simulation because the number of patterns can be reduced by a factor of n, the number of machines, and the faults detected by any machine can be dropped through the communication of the network. For a sequential circuit, there is dependence between test patterns. The state of the circuit depends on the previous patterns applied to the circuit. When the patterns are partitioned into several groups for distributed fault simulation, a sub-fault simulation process for each machine is needed to simulate the circuit into the same state of its previous machine in order to obtain the right results. Hence, in this work, each machine firstly performs the true value simulation with the patterns, which are performed the fault simulation by the previous machines. As the fault simulation is partitioned as above, the state of the good machine is the same as that of the normal fault simulation. A mathematical model is presented to predict the performance of this pattern-partitioning distributed fault simulation. The fault simulator used in is SEESIM, which is a fast sequential circuit fault simulator based on single event equivalence. The statistics of the speedup of the distributed fault simulation with 2000 random patterns and patterns generated by an ATPG, respectively, are shown. It is shown that the speedup ratio increases with the number of machines, and the speedup can exceed the number of machines for some circuits.<>
{"title":"Distributed fault simulation for sequential circuits by pattern partitioning","authors":"Wen Ching Wu, Chung-Len Lee, Jwu-E Chen, Won Yih Lin","doi":"10.1109/EDTC.1994.326801","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326801","url":null,"abstract":"The authors target the pattern partitioning on the distributed fault simulation because the number of patterns can be reduced by a factor of n, the number of machines, and the faults detected by any machine can be dropped through the communication of the network. For a sequential circuit, there is dependence between test patterns. The state of the circuit depends on the previous patterns applied to the circuit. When the patterns are partitioned into several groups for distributed fault simulation, a sub-fault simulation process for each machine is needed to simulate the circuit into the same state of its previous machine in order to obtain the right results. Hence, in this work, each machine firstly performs the true value simulation with the patterns, which are performed the fault simulation by the previous machines. As the fault simulation is partitioned as above, the state of the good machine is the same as that of the normal fault simulation. A mathematical model is presented to predict the performance of this pattern-partitioning distributed fault simulation. The fault simulator used in is SEESIM, which is a fast sequential circuit fault simulator based on single event equivalence. The statistics of the speedup of the distributed fault simulation with 2000 random patterns and patterns generated by an ATPG, respectively, are shown. It is shown that the speedup ratio increases with the number of machines, and the speedup can exceed the number of machines for some circuits.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129003050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326830
J. C. Yang, G. Micheli, M. Damiani
We introduce a framework in which design information can be represented using an automaton model. We present a novel scheduling algorithm under environmental constraints where both the design and constraints are represented using automata. This model offers the advantage of supporting different constraints (e.g. timing, resource, synchronization, etc.) with a uniform formalism. All feasible schedules are captured with a single product automaton. The automaton is constructed and traversed using efficient BDD-based implicit state-traversal techniques. We present an algorithm that generates a minimum-latency schedule. This approach is able to exploit degrees of freedom among interacting components of a multi-module system during scheduling.<>
{"title":"Scheduling with environmental constraints based on automata representations","authors":"J. C. Yang, G. Micheli, M. Damiani","doi":"10.1109/EDTC.1994.326830","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326830","url":null,"abstract":"We introduce a framework in which design information can be represented using an automaton model. We present a novel scheduling algorithm under environmental constraints where both the design and constraints are represented using automata. This model offers the advantage of supporting different constraints (e.g. timing, resource, synchronization, etc.) with a uniform formalism. All feasible schedules are captured with a single product automaton. The automaton is constructed and traversed using efficient BDD-based implicit state-traversal techniques. We present an algorithm that generates a minimum-latency schedule. This approach is able to exploit degrees of freedom among interacting components of a multi-module system during scheduling.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129360380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326892
Lakshmikanth Ghatraju, M. Abd-El-Barr, C. McCrosky
A technique for the synthesis of two-level and nested logic from recursive behavioral specifications is presented. The two-level circuits derived are optimal (up to product term sharing). Different specifications of the same function always yield the same hardware. Any recursive first-order function can be synthesized without a stack /spl minus/ no other high-level synthesis systems have demonstrated this capability. The technique is extended to synthesize circuits for a wide range of sequential circuits. The formal techniques used are based on domain theory and "frontiers" algorithms.<>
{"title":"High-level synthesis of digital circuits by finding fixpoints","authors":"Lakshmikanth Ghatraju, M. Abd-El-Barr, C. McCrosky","doi":"10.1109/EDTC.1994.326892","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326892","url":null,"abstract":"A technique for the synthesis of two-level and nested logic from recursive behavioral specifications is presented. The two-level circuits derived are optimal (up to product term sharing). Different specifications of the same function always yield the same hardware. Any recursive first-order function can be synthesized without a stack /spl minus/ no other high-level synthesis systems have demonstrated this capability. The technique is extended to synthesize circuits for a wide range of sequential circuits. The formal techniques used are based on domain theory and \"frontiers\" algorithms.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124591417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326827
H. Wittmann, M. Henftling
This paper presents an efficient method of handling a large number of paths during path-delay fault testing. Instead of handling the corresponding set of signals, an identifier is derived for every path. We handle up to three billion paths because the memory requirement is only about three bits per path. Compared to former approaches, experimental results show fast access, small memory requirements, and negligible CPU-times for the management of huge path sets.<>
{"title":"Efficient path identification for delay testing /spl minus/ time and space optimization","authors":"H. Wittmann, M. Henftling","doi":"10.1109/EDTC.1994.326827","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326827","url":null,"abstract":"This paper presents an efficient method of handling a large number of paths during path-delay fault testing. Instead of handling the corresponding set of signals, an identifier is derived for every path. We handle up to three billion paths because the memory requirement is only about three bits per path. Compared to former approaches, experimental results show fast access, small memory requirements, and negligible CPU-times for the management of huge path sets.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124239182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326888
I. Harris, A. Orailoglu
Partial-intrusion BIST reduces area overhead and increases chip performance by reducing the number of test registers, but it requires a test schedule definition. The scheduling of the tests impacts directly the test application time. This paper presents a novel model of the test plan scheduling problem for partial-intrusion BIST circuits. Test application time is reduced by performing scheduling to allow the execution of test plans in a pipelined fashion. Test scheduling conflicts are avoided by exploiting the parallelism which is revealed by a flexible test representation; consequently, test concurrency is increased. Computational efficiency is gained by performing incremental, subtractive heuristic test scheduling decisions. The effects of each test decision are rigorously propagated, limiting the test scheduling possibilities to only those which lead to a feasible scheduling solution. Experimental results show that high levels of test concurrency are achieved in a computationally efficient manner by limiting the state of the scheduling search space using conflict probability estimation and rigorous pruning of infeasible test options.<>
{"title":"Fine-grained concurrency in test scheduling for partial-intrusion BIST","authors":"I. Harris, A. Orailoglu","doi":"10.1109/EDTC.1994.326888","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326888","url":null,"abstract":"Partial-intrusion BIST reduces area overhead and increases chip performance by reducing the number of test registers, but it requires a test schedule definition. The scheduling of the tests impacts directly the test application time. This paper presents a novel model of the test plan scheduling problem for partial-intrusion BIST circuits. Test application time is reduced by performing scheduling to allow the execution of test plans in a pipelined fashion. Test scheduling conflicts are avoided by exploiting the parallelism which is revealed by a flexible test representation; consequently, test concurrency is increased. Computational efficiency is gained by performing incremental, subtractive heuristic test scheduling decisions. The effects of each test decision are rigorously propagated, limiting the test scheduling possibilities to only those which lead to a feasible scheduling solution. Experimental results show that high levels of test concurrency are achieved in a computationally efficient manner by limiting the state of the scheduling search space using conflict probability estimation and rigorous pruning of infeasible test options.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121414471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326889
A. P. Stroele
When test responses are compacted, even some erroneous response sequences can lead to the error-free signature. This phenomenon of aliasing has been studied thoroughly using the assumption that errors in successive responses are statistically independent. In this paper signature analysis and aliasing are investigated for the test responses of sequential circuits with reset where errors can be correlated both in space and time. The probability of aliasing in a signature analyzer with an irreducible characteristic polynomial of degree k tends to 2/sup /spl minus/k/ as test lengths increase.<>
{"title":"Signature analysis for sequential circuits with reset","authors":"A. P. Stroele","doi":"10.1109/EDTC.1994.326889","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326889","url":null,"abstract":"When test responses are compacted, even some erroneous response sequences can lead to the error-free signature. This phenomenon of aliasing has been studied thoroughly using the assumption that errors in successive responses are statistically independent. In this paper signature analysis and aliasing are investigated for the test responses of sequential circuits with reset where errors can be correlated both in space and time. The probability of aliasing in a signature analyzer with an irreducible characteristic polynomial of degree k tends to 2/sup /spl minus/k/ as test lengths increase.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130107673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326811
P. Camurati, Fulvio Corno, P. Prinetto, C. Bayol, B. Soulas
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level.<>
{"title":"System-level modeling and verification: a comprehensive design methodology","authors":"P. Camurati, Fulvio Corno, P. Prinetto, C. Bayol, B. Soulas","doi":"10.1109/EDTC.1994.326811","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326811","url":null,"abstract":"Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130206159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326870
P. Coulomb, F. Pogodalla
This paper presents a fast Fourier transform ASIC designed to be used on a DSP expansion board for a PC. From specification to test all steps in the ASIC design were made by 3rd year engineering school students. This project formed part of the practical work of the ASIC design courses in the ENSIMAG/ENSERG Architecture Department. The final chip implements the direct and reverse FFT algorithms, external buses arbitration, host interface, converters and memory management. Running at 25 MHz, this 30000 transistor ASIC can perform realtime signal processing on 44 kHz sample rate audio signals.<>
{"title":"PLFP256 a pipelined Fourier processor","authors":"P. Coulomb, F. Pogodalla","doi":"10.1109/EDTC.1994.326870","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326870","url":null,"abstract":"This paper presents a fast Fourier transform ASIC designed to be used on a DSP expansion board for a PC. From specification to test all steps in the ASIC design were made by 3rd year engineering school students. This project formed part of the practical work of the ASIC design courses in the ENSIMAG/ENSERG Architecture Department. The final chip implements the direct and reverse FFT algorithms, external buses arbitration, host interface, converters and memory management. Running at 25 MHz, this 30000 transistor ASIC can perform realtime signal processing on 44 kHz sample rate audio signals.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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