Hiroaki Igarashi, Youhua Shi, M. Yanagisawa, N. Togawa
{"title":"Throughput driven check point selection in suspicious timing error prediction based designs","authors":"Hiroaki Igarashi, Youhua Shi, M. Yanagisawa, N. Togawa","doi":"10.1109/LASCAS.2014.6820280","DOIUrl":null,"url":null,"abstract":"In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection will affect both the maximal operation frequency and the suspicious timing error overestimation rate, both of which have an effect on the overall throughput, thus an analysis on the check point selection is also given. In our work, the circuit can be overclocked by a factor of 2 or more with ignorable area overhead while guarantees the always-correct output.","PeriodicalId":235336,"journal":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE 5th Latin American Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2014.6820280","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a throughput-driven design technique is proposed, in which a suspicious timing error prediction circuit is inserted to monitor the signal transitions at some selected check points. Unlike previous works where timing errors are detected after their occurrence, the proposed method tries to use the real intermediate signal transitions for timing error prediction. The check point selection will affect both the maximal operation frequency and the suspicious timing error overestimation rate, both of which have an effect on the overall throughput, thus an analysis on the check point selection is also given. In our work, the circuit can be overclocked by a factor of 2 or more with ignorable area overhead while guarantees the always-correct output.