Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation

Abstract

Diagnosis of integrated circuits is an arduous process. Tools are needed which aid developers locating circuit's faulty parts faster. In this work path delay faults are considered. A simulation based diagnosis algorithm using diagnostic test patterns is introduced for locating the cause of the delay fault. Initial paths are segmented to improve the diagnosis accuracy. For each segment, additional diagnostic test patterns are generated using a solver for Boolean Satisfiability. The experimental results show that a significant improvement of the diagnostic accuracy is achievable with our approach.