Timing models for high-level synthesis

Abstract

A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.<>