Yunlong Li, G. Karve, P. Malinowski, J. Kim, Epimitheas Georgitzikis, V. Pejović, M. Lim, L. M. Hagelsieb, R. Puybaret, I. Lieberman, Jiwon Lee, D. Cheyns, P. Heremans, H. Osman, D. Tezcan
{"title":"Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors","authors":"Yunlong Li, G. Karve, P. Malinowski, J. Kim, Epimitheas Georgitzikis, V. Pejović, M. Lim, L. M. Hagelsieb, R. Puybaret, I. Lieberman, Jiwon Lee, D. Cheyns, P. Heremans, H. Osman, D. Tezcan","doi":"10.1109/vlsitechnologyandcir46769.2022.9830334","DOIUrl":null,"url":null,"abstract":"Monolithic integration of colloidal quantum dot (CQD) thin-film on 200 mm CMOS wafers is demonstrated. Full pixelation of CQD thin-film photodiodes at wafer level is presented for the first time. We show a low-temperature process flow compatible with standard CMOS fab equipment. The self-aligned pixelation approach is an improvement over a conventional way of having a thin-film absorber layer on pixelated bottom electrodes, and it enables crosstalk reduction as well as multi-stack arrays.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830334","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Monolithic integration of colloidal quantum dot (CQD) thin-film on 200 mm CMOS wafers is demonstrated. Full pixelation of CQD thin-film photodiodes at wafer level is presented for the first time. We show a low-temperature process flow compatible with standard CMOS fab equipment. The self-aligned pixelation approach is an improvement over a conventional way of having a thin-film absorber layer on pixelated bottom electrodes, and it enables crosstalk reduction as well as multi-stack arrays.