Modeling and simulation of wideband low jitter frequency synthesizer

A. Telba
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引用次数: 5

Abstract

This paper presents modeling and simulation of a wideband low jitter frequency synthesizer. The proposed system uses two phase-locked loops (PLLs) connected in cascade. The first PLL uses a voltage-controlled crystal oscillator (VCXO) to eliminate the input jitter and the second one is a wideband PLL. One important advantage of using the proposed system is that it uses only one VCXO for multiple carrier frequencies, while reducing the jitter considerably. The MATLAB Simulink simulation results show that the jitter could be minimized while working at different carrier frequencies.
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宽带低抖动频率合成器的建模与仿真
本文介绍了一种宽带低抖动频率合成器的建模与仿真。该系统采用两个锁相环级联连接。第一个锁相环使用压控晶体振荡器(VCXO)来消除输入抖动,第二个锁相环是宽带锁相环。使用该系统的一个重要优点是它只使用一个VCXO来处理多个载波频率,同时大大减少了抖动。MATLAB Simulink仿真结果表明,在不同载波频率下工作时,抖动可以被最小化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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