Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164164
Vijendra Singh, Simran Choudhary
This paper addresses an attempt to evolve Genetic Algorithm by a particular modified Partially Mapped Crossover method to make it able to solve the Traveling Salesman Problem. Which is type of NP-hard combinatorial optimization problems. The main objective is to look a better GA such that solves TSP with shortest tour. First we solve the TSP by using PMX (Goldberg [1]) and then a modified PMX to evolve a GA.
{"title":"Genetic algorithm for Traveling Salesman Problem: Using modified Partially-Mapped Crossover operator","authors":"Vijendra Singh, Simran Choudhary","doi":"10.1109/MSPCT.2009.5164164","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164164","url":null,"abstract":"This paper addresses an attempt to evolve Genetic Algorithm by a particular modified Partially Mapped Crossover method to make it able to solve the Traveling Salesman Problem. Which is type of NP-hard combinatorial optimization problems. The main objective is to look a better GA such that solves TSP with shortest tour. First we solve the TSP by using PMX (Goldberg [1]) and then a modified PMX to evolve a GA.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115009650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164237
Nisha, Avneesh Mittal, O. P. Sharma, Nitu Dhyani, Vijay Sharma, A. Kapoor, T. Saxena
Tuning of the PID controller in a varying environment is extremely difficult. For this purpose one has to use the adaptive PID controller. In the present paper a novel method for fast tuning of the PID controller has been presented and implemented on designed and developed hardware around the 89C51 microcontroller. Varying environment in the very old existing MLW-MK70, former East German bath has been created with the help of two microcontrollers. The artificial neural network (ANN) has been used to tune the PID parameters. The software has been written in Visual BASIC5.0 language.
{"title":"Tuning of PID parameters using artificial neural network","authors":"Nisha, Avneesh Mittal, O. P. Sharma, Nitu Dhyani, Vijay Sharma, A. Kapoor, T. Saxena","doi":"10.1109/MSPCT.2009.5164237","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164237","url":null,"abstract":"Tuning of the PID controller in a varying environment is extremely difficult. For this purpose one has to use the adaptive PID controller. In the present paper a novel method for fast tuning of the PID controller has been presented and implemented on designed and developed hardware around the 89C51 microcontroller. Varying environment in the very old existing MLW-MK70, former East German bath has been created with the help of two microcontrollers. The artificial neural network (ANN) has been used to tune the PID parameters. The software has been written in Visual BASIC5.0 language.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115370253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164205
M. S. Khan, Rehan Ahmad, Tauseef Ahmad, M. Qadeer
The Bluetooth specification describes a robust and powerful technology for short-range wireless communication. Unfortunately, the specification is immense and complicated, presenting a formidable challenge for novice developers. This paper is concerned with Recording video from Mobile Phone to Desktop computers and Laptops. Users could be able to Record huge data and stored in the computers within its range of Bluetooth dongle. Through we can create a Bluetooth PAN (Piconet) in which mobile computers can dynamically connect to master and communicate with other slave. Dynamically we can select any Mobile computer and data transferred into that. Mobile has limited storage capacity with respect to computers, Therefore computers should be prefer to store Recorded data.
{"title":"Real time streaming video over Bluetooth network","authors":"M. S. Khan, Rehan Ahmad, Tauseef Ahmad, M. Qadeer","doi":"10.1109/MSPCT.2009.5164205","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164205","url":null,"abstract":"The Bluetooth specification describes a robust and powerful technology for short-range wireless communication. Unfortunately, the specification is immense and complicated, presenting a formidable challenge for novice developers. This paper is concerned with Recording video from Mobile Phone to Desktop computers and Laptops. Users could be able to Record huge data and stored in the computers within its range of Bluetooth dongle. Through we can create a Bluetooth PAN (Piconet) in which mobile computers can dynamically connect to master and communicate with other slave. Dynamically we can select any Mobile computer and data transferred into that. Mobile has limited storage capacity with respect to computers, Therefore computers should be prefer to store Recorded data.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115663880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164188
K. Geetha, V. K. Ananthashayana
A special class of multiplierless transforms for computing discrete cosine transform (DCT) is introduced. This algorithm is completely multiplierless to compute an N-point DCT using Ramanujan Number of order -1 and order-2. The algorithm requires evaluation of Cosine angles which are multiples of 2π/N. If the transform size N is a Ramanujan Number and if 2π/N ≅ 2−a, then the cosine functions can be computed by shifts and adds employing Chebyshev type of recursion. In this paper, an analytical extension of the algorithm is made for 2-D Ramanujan DCT for image coding applications.
{"title":"Fast multiplierless recursive transforms using Ramanujan numbers","authors":"K. Geetha, V. K. Ananthashayana","doi":"10.1109/MSPCT.2009.5164188","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164188","url":null,"abstract":"A special class of multiplierless transforms for computing discrete cosine transform (DCT) is introduced. This algorithm is completely multiplierless to compute an N-point DCT using Ramanujan Number of order -1 and order-2. The algorithm requires evaluation of Cosine angles which are multiples of 2π/N. If the transform size N is a Ramanujan Number and if 2π/N ≅ 2−a, then the cosine functions can be computed by shifts and adds employing Chebyshev type of recursion. In this paper, an analytical extension of the algorithm is made for 2-D Ramanujan DCT for image coding applications.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164210
Dhananjay Singh, Sanjay Singh, Madhusudan Singh, Hsein-Ping Kew, Doowon Jeoung, U. Tiwary, Hoon-Jae Lee
A LoWPAN is a communication network that allows wireless connectivity in varies applications due to its unique advantages. LoWPANs can be benefit from IP and thus IPv6 networking formed. The combination of IP over LoWPAN is 6lowpan (IPv6 over low power wireless personal area networks). IP in WSNs can eliminate the need of translation gateway and other similar devices used in current WSNs. It allows direct access of a commercial PDA running J2ME application to monitor data. Low-power wireless personal area networks (LoWPANs) conform to the IEEE 802.15.4-2003 standard. In this paper we propose prototype for global homecare monitoring system and design MAC for patient data. Results show the performance biomedical data delivery to the gateway. The patient freely moves inside to his personal home area and doctor can continuously monitor to his patient's signal. The biomedical ECG signals are transmitted to 6lowpan and then routed to the gateway internet using routing protocols.
低pan是一种通信网络，由于其独特的优势，它允许在各种应用中进行无线连接。lowpan可以受益于IP，从而形成IPv6网络。IP over LoWPAN的组合是6lowpan (IPv6 over低功耗无线个人区域网络)。无线传感器网络中的IP可以消除当前无线传感器网络中对转换网关和其他类似设备的需求。它允许直接访问运行J2ME应用程序的商业PDA来监视数据。低功耗无线个人区域网络(lowpan)符合IEEE 802.15.4-2003标准。本文提出了全球家庭护理监测系统的原型，并设计了患者数据的MAC。结果表明，该网关实现了生物医学数据的高效传输。病人可以自由地进入自己的家庭区域，医生可以持续监测病人的信号。生物医学心电信号被传输到6lowpan，然后通过路由协议路由到网关互联网。
{"title":"IP-based ubiquitous sensor network for in-home healthcare monitoring","authors":"Dhananjay Singh, Sanjay Singh, Madhusudan Singh, Hsein-Ping Kew, Doowon Jeoung, U. Tiwary, Hoon-Jae Lee","doi":"10.1109/MSPCT.2009.5164210","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164210","url":null,"abstract":"A LoWPAN is a communication network that allows wireless connectivity in varies applications due to its unique advantages. LoWPANs can be benefit from IP and thus IPv6 networking formed. The combination of IP over LoWPAN is 6lowpan (IPv6 over low power wireless personal area networks). IP in WSNs can eliminate the need of translation gateway and other similar devices used in current WSNs. It allows direct access of a commercial PDA running J2ME application to monitor data. Low-power wireless personal area networks (LoWPANs) conform to the IEEE 802.15.4-2003 standard. In this paper we propose prototype for global homecare monitoring system and design MAC for patient data. Results show the performance biomedical data delivery to the gateway. The patient freely moves inside to his personal home area and doctor can continuously monitor to his patient's signal. The biomedical ECG signals are transmitted to 6lowpan and then routed to the gateway internet using routing protocols.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125115120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164213
Pranamita Basu, M. Manjunatha
This paper describes the VHDL modelling and simulation of parallel-beam filtered backprojection algorithm to be used for image reconstruction in CT (computed tomography). The algorithm being highly data intensive and computationally extensive requires a lot of time for execution and hence it necessitates hardware implementation for real-time processing. So the VHDL model can be implemented on reconfigurable hardware. Due to memory constraints a smaller size image has been implemented on FPGA while the VHDL model has been designed for a 512×512 image which can be implemented on FPGA using offchip memory blocks.
{"title":"VHDL modelling and simulation of parallel-beam filtered backprojection for CT image reconstruction","authors":"Pranamita Basu, M. Manjunatha","doi":"10.1109/MSPCT.2009.5164213","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164213","url":null,"abstract":"This paper describes the VHDL modelling and simulation of parallel-beam filtered backprojection algorithm to be used for image reconstruction in CT (computed tomography). The algorithm being highly data intensive and computationally extensive requires a lot of time for execution and hence it necessitates hardware implementation for real-time processing. So the VHDL model can be implemented on reconfigurable hardware. Due to memory constraints a smaller size image has been implemented on FPGA while the VHDL model has been designed for a 512×512 image which can be implemented on FPGA using offchip memory blocks.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126627069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5426444
M. Torabi, A. Vafaee, N. Movahhedinia
In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.
{"title":"A fast architecture for deblocking filter in H.264/AVC using clock cycles saving process","authors":"M. Torabi, A. Vafaee, N. Movahhedinia","doi":"10.1109/MSPCT.2009.5426444","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5426444","url":null,"abstract":"In this paper a fast architecture for Deblocking Filter in H.264/AVC video coding standard is presented. This architecture consists of a jump circuit which can increase the processing speed. To reduce the system complexity, we consider a single port external memory to be connected to our architecture. Accessing to the external memory is reduced by reusing stored blocks. Filtering operation is concurrent with reading/writing blocks. Simulation results show that the processing cycle count of the proposed architecture has decreased comparing to other similar architectures.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122672405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164159
S. Erfanian, V. Vakili
In radar signal processing distinction of false targets from real targets and fixing their rate in different radar environments is desirable. In this paper, at first, Switching Constant False Alarm Rate (S-CFAR) processor has been improved to achieve Improved SCFAR in order to fix the false alarm rate not only in homogenous environment only with thermal noise but also in non-homogenous environment, consisting clutter edge and multiple targets in the background Gaussian noise. Then in continue, a new CFAR detector which is composed of an excisior and a Switching CFAR detector, in an environment with K distribution, has been introduced. The new detector is named an Excision Switching CFAR (EXS-CFAR). The equations have been achieved by assuming the targets in Swerling I and closed form. The simulation results confirm that the introduced processors can fix the false alarm rate in both homogenous and non-homogenous environment with less detection loss. In addition, this method is simpler in implementation comparing with other samples ordering processors.
{"title":"Analysis of some CFAR detectors in nonhomogenous environments based on switching algorithm","authors":"S. Erfanian, V. Vakili","doi":"10.1109/MSPCT.2009.5164159","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164159","url":null,"abstract":"In radar signal processing distinction of false targets from real targets and fixing their rate in different radar environments is desirable. In this paper, at first, Switching Constant False Alarm Rate (S-CFAR) processor has been improved to achieve Improved SCFAR in order to fix the false alarm rate not only in homogenous environment only with thermal noise but also in non-homogenous environment, consisting clutter edge and multiple targets in the background Gaussian noise. Then in continue, a new CFAR detector which is composed of an excisior and a Switching CFAR detector, in an environment with K distribution, has been introduced. The new detector is named an Excision Switching CFAR (EXS-CFAR). The equations have been achieved by assuming the targets in Swerling I and closed form. The simulation results confirm that the introduced processors can fix the false alarm rate in both homogenous and non-homogenous environment with less detection loss. In addition, this method is simpler in implementation comparing with other samples ordering processors.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130558480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164191
M. S. Ansari, S. J. Arif
Ranking or ordering of a set of numbers based on their relative magnitudes is a fundamental operation in computing. In this paper, we propose a neural circuit for ranking a given set of numbers. The proposed network does not require any feedback connection, requires fewer neurons, and fewer interconnections between neurons as compared to existing schemes. Moreover, the numbers to be sorted are applied as inputs to the circuit unlike some existing schemes which impress the numbers to be sorted as initial conditions on the network. Results of PSPICE simulation confirm the theory proposed.
{"title":"A feed-forward neural circuit for ranking N numbers using O (N) neurons","authors":"M. S. Ansari, S. J. Arif","doi":"10.1109/MSPCT.2009.5164191","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164191","url":null,"abstract":"Ranking or ordering of a set of numbers based on their relative magnitudes is a fundamental operation in computing. In this paper, we propose a neural circuit for ranking a given set of numbers. The proposed network does not require any feedback connection, requires fewer neurons, and fewer interconnections between neurons as compared to existing schemes. Moreover, the numbers to be sorted are applied as inputs to the circuit unlike some existing schemes which impress the numbers to be sorted as initial conditions on the network. Results of PSPICE simulation confirm the theory proposed.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129192578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-03-14DOI: 10.1109/MSPCT.2009.5164235
Syed Manzoor Qasim, S. A. Abbasi, B. Almashary
Algorithms used in signal and image processing applications are computationally intensive. For optimized hardware realization of such algorithms with efficient utilization of available resources, an in-depth knowledge of the targeted field programmable gate array (FPGA) technology is required. This paper presents an overview of the architectures and technologies used in modern FPGAs. A case study of most popular and widely used state-of-the-art commercial FPGA technologies from Xilinx and Altera is also presented. Three-Dimensional (3D)-FPGA architecture is also discussed.
{"title":"An overview of advanced FPGA architectures for optimized hardware realization of computation intensive algorithms","authors":"Syed Manzoor Qasim, S. A. Abbasi, B. Almashary","doi":"10.1109/MSPCT.2009.5164235","DOIUrl":"https://doi.org/10.1109/MSPCT.2009.5164235","url":null,"abstract":"Algorithms used in signal and image processing applications are computationally intensive. For optimized hardware realization of such algorithms with efficient utilization of available resources, an in-depth knowledge of the targeted field programmable gate array (FPGA) technology is required. This paper presents an overview of the architectures and technologies used in modern FPGAs. A case study of most popular and widely used state-of-the-art commercial FPGA technologies from Xilinx and Altera is also presented. Three-Dimensional (3D)-FPGA architecture is also discussed.","PeriodicalId":179541,"journal":{"name":"2009 International Multimedia, Signal Processing and Communication Technologies","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114019638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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