A Novel Design of DDR-based Data Acquisition Storage Module in a Digitizer

Abstract

A DDR-based data acquisition storage module designed for a high-capacity high sampling rate digitizer is described in this paper. The architecture allows two identical data acquisition channels to record consecutive data streams in two acquisition modes-sequence mode in 256k points and single mode in 64M points per channel-at a sampling rate ranging from 40MSa/s to 400MSa/s. The prototype is accomplished by unique DDR SDRAM controller cores embedded in a FPGA device, long acquisition memories combined with a time interleaved ADC system. Also, a flexible trigger mechanism is imported to the module, which is a crucial component to a digitizer, enabling a precise trigger capture with adjustable pre-triggering depth.