{"title":"Design of the Tera MTA integrated circuits","authors":"M. Howard, A. Kopser","doi":"10.1109/GAAS.1997.628228","DOIUrl":null,"url":null,"abstract":"The Tera MTA (Multi-Threaded Architecture) computer system is a scalable shared memory multiprocessor implemented in semi-custom GaAs ICs. This paper gives an overview of attributes of the Tera MTA architecture that influenced the chip design. It then describes the IC technology selection, design methodology, and yield enhancements.","PeriodicalId":299287,"journal":{"name":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1997.628228","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The Tera MTA (Multi-Threaded Architecture) computer system is a scalable shared memory multiprocessor implemented in semi-custom GaAs ICs. This paper gives an overview of attributes of the Tera MTA architecture that influenced the chip design. It then describes the IC technology selection, design methodology, and yield enhancements.
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