A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models

Abstract

Using memory models in a hardware-assisted acceleration/emulation environment, as contrasted with a software simulation environment, is often infused with some very specific problems. This paper describes a novel, yet reliable, methodology to capture the essential functionalities and timings, from a chip designer's perspective, of commonly used embedded memories. The captured data is placed in a structural template for creating a knowledge base, which is transformed into targeted hardware-ready memories. A testbench is also created to verify the new models against the original behavioral models. This methodology has been used for years in many real design projects with great success.