Study on the origin of dc-to-RF dispersion effects in GaAs- and GaN-based beterostructure FETs

Abstract

Deep-level-induced dc-to-RF dispersion effects, such as gate lag, transconductance (g,) frequency dispersion, and drain-current (Io) collapse, continue to represent a serious limitation for many power microwave FETs based on compound semiconductors, principally because of the associated depadation of output-power density at operating frequencies. Io devices with optimized vertical structure growth, dispersion effects, ifpresent, are induced by deep-level traps at the ungated device surface. The influence of surface traps can actually be minimized by reducing gate-recess extension and/or inter-electrode spacings, but, in doing so, a penalty must be accepted in terms of gate-drain breakdown voltage reduction, the inherent trade-off between de-to-RF dispersion immunity and high-voltage capability making the physical comprehension of dispersion effects crucial for proper procesddevice optimization. Unfortunately, in spite of extensive research efforts, the physics underlying surface-trap action has not been completely clarified yet. The explanation which is more conventionally accepted is that electrons leaking from the gate metal are trappedldetrapped by surface deep levels. Initially proposed for GaAs MESFETs [I], this explanation has been extended to other 111-V FETs [2,3] and, more recently, adopted for GaN-based devices [4]. In ihepveseni work a consisieni sei ofrxperirnental and numerical resulrs ure prrsenied, addressing dc-io-RF dispersion erecis in FETS of two direreeni iechnologies, naniely AIGaAdGaAs lreierosiructure FETs (HFETs) and AIGoN/GuN IIEMTs. Numerical device siniirlations siimesi ihni, d~erenrlyfrom whui coninronl~~ assured. suiface 1rap.s can hehuve. during the switching iransienis of hoih device i.vpes, as hole irups inierading with holes aifracted a! the ungated surfice by surface band bending. Devices used for this work are I ) double recess, doped-channel AIGaAs/GaAs IlFETs featuring different ungated gate-source and gate-drain recess lengths (ALgl=O, 0.1, 0.23 pm), a gate width of 200 pm and D gate length (L,) that varies with ALgl as L, =0.7-2.ALgl; 2) unpassivated AIGaNGaN HEMTs grown by MOCVD on S i c substrates and characterized by a gate widtWlength of 150pm/O.7pm and by gate-source and gate-drain spacings of 0.7 pm and 2 pm, respectively. As far as the AIGaAdGaAs HFETs are concerned, obtained results can be outlined as follows. 1) Gate lag, Io collapse under pulsed-Vos operation, and transconductance (g,,,) frequency dispersion are negligible in samples having ALgl=O, while they increasingly affect device operation at increasing ALgl. This Fdct indicates that deep levels responsible for the observed dispersion effects are located at the ungated recess surface. 2) Gate lag depends markedly on the adopted rum-off VGs value (V,s.o,,) and drain bias (VDD). More specifically, gate-lag effects diminish (i) by making Vos.ovF less negative and (ii) by increasing VDo, see Fig. 1. 3) Temperature (T) impacts gate lag differently depending on the drain bias. More specifically, increasing T makes the turn-on faster at low VDD, see Fig. 2, while slightly delaying it at high VDU, see Fig. 3. From the temperature dependence of the turn-on time constant at low VDD, an activation energy EPL=0.S6 eV is extracted, see Fig. 2. 4) Two-dimensional (2-D) hydrodynamic device simulations accounting for acceptor-like traps at the ungated recess surface predict dispersion phenomena in good agreement with experiments. provided that surface traps are energetically placed at ET=EV+E,"L. Under this hypothesis. tum on is limited by hole capture by surface traps, leading to decrease in negative trapped charge and consequent Io increase. 5) Simulations reproduce correctly the bias dependence of gate lag, compare Figs. 1 and 4. They show in particular that gate lag is attenuated at increasing VDs. as a consequence of impact-ionization-induced hole generation and consequent surface hole density (ps) increase. 6) Increasing T at low Vos enhances ps. thus resulting in shorter tum-on transient, see Figs. Sa and 2. At high VUS. channel impact ionization comes into play, raising significantly ps over its low-Vos values. Under these conditions, increasing T leads to reduced impact-ionization rate in the GaAs channel and, consequently, to reduced ps. This explain why, at high Vu$, the Io rise time increases at increasing T, see Figs. 5b and 3. Results obtained from AIGaN/GaN HEMTs can be summarized as follows. a) Significant gale-lag and To collapse phenomena are measured under pulsed-VGs operation, see Fig. 6. From the temperature dependence of gate-lag waveforms an activation energy of 0.3 eV is extracted, see Fig. 7. b) Dispersion phenomena are reproduced by 2-D drift-diffision simulations, accounting for fixed polarization charges at the AlGaN/GaN hetero-interface aud the ungated AlGaN surface and for donor-like surface traps at the ungated AlGaN surface, see Fig. 8. Surface traps are energetically placed at E,= Ev+0.3 eV. Band are strongly upward bent at the ungated AlGaN surface owing to the negative polarization charge. Similarly to what found in AICaAdGaAs IIFETs, simulations attribute gate lag and pulsed-I, collapse to the hole-trap behavior of surface deep levels. References. [ I ] S.R. Blight et al., IEEE Trans. Electr. Dev., vol. 33(10), p. 1447, 1986. [2] I.C. Huang et al., IEEE Trans. Microwave Theory Tech., vol. 41(5), p. 752,1993. [3] W. Kruppa and J. B. Boos, IEEE Trans. Electr. Dev.. vol. 44(5), p. 68, 1997.[4] R. Veturyetal., IEEETrans. Electr. Dev., vol. 48(3),p. 560,2001.