Pub Date : 2004-07-01DOI: 10.1109/GAASRW.2003.183764
P. Ersland, H. Jen, Xinxing Yang
Abstract We report the results of DC biased life tests performed on gallium arsenide pseudomorphic high electron mobility transistor (GaAs pHEMT) switches under elevated temperature and humidity conditions. The goal of this work was to determine whether the acceleration factors typically reported for silicon technologies are also appropriate for GaAs technologies. Toward that end we performed tests at three different temperatures and two different humidity conditions. Failure distributions were generated for each life test, and the results applied to an acceleration model commonly used for HAST. We determined the activation energy for the failures observed during these tests to be 0.81 eV; similar to values commonly reported for HAST tests of silicon technologies. In contrast, our results show significantly stronger stress acceleration due to relative humidity (RH−10.7) than is typically reported for silicon (RH−3.0). Examples of typical visual and electrical device failure signatures are shown.
{"title":"Lifetime acceleration model for HAST tests of a pHEMT process","authors":"P. Ersland, H. Jen, Xinxing Yang","doi":"10.1109/GAASRW.2003.183764","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183764","url":null,"abstract":"Abstract We report the results of DC biased life tests performed on gallium arsenide pseudomorphic high electron mobility transistor (GaAs pHEMT) switches under elevated temperature and humidity conditions. The goal of this work was to determine whether the acceleration factors typically reported for silicon technologies are also appropriate for GaAs technologies. Toward that end we performed tests at three different temperatures and two different humidity conditions. Failure distributions were generated for each life test, and the results applied to an acceleration model commonly used for HAST. We determined the activation energy for the failures observed during these tests to be 0.81 eV; similar to values commonly reported for HAST tests of silicon technologies. In contrast, our results show significantly stronger stress acceleration due to relative humidity (RH−10.7) than is typically reported for silicon (RH−3.0). Examples of typical visual and electrical device failure signatures are shown.","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129066964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-07-01DOI: 10.1109/GAASRW.2003.183769
B. Paine, T. Perham, S. Thomas
Abstract We have used high-resolution transmission electron microscopy (HRTEM), with focused-ion-beam preparation of foils, to study InP HBT devices, both as-fabricated and after aging in life tests. The technology is HRL's G1 process. We found that even after aging for the equivalent of 2 × 107 h under normal operating conditions, the visible damage is extremely benign: the base and emitter contacts are completely intact, there is no evidence of significant Au or Pt migration into the semiconductor, and minor crystal disorder that develops does not extend more than 100 nm below the metal–semiconductor interfaces. Except for these regions, the intrinsic devices are completely devoid of any anomalous features, to within the 0.3 nm resolution limit of the measurements. These observations provide strong evidence that failure mechanisms involving migration of metal from the ohmic contacts, or extended crystal defects, do not limit the reliability of this technology. The small disorder under the base contacts can probably explain the increases of gain (β) observed early in our life tests, and small increases in the base-collector leakage occurring later in the life tests. The minor disorder under the emitter contacts can probably explain the moderate increase of emitter resistance observed late in our life tests. But the mechanism for the eventual decline in β, observed after a long period of stress, for the equivalent of 107 h of normal operation, is not apparent from the HRTEM images.
{"title":"High-resolution transmission electron microscopy on aged inp HBTs","authors":"B. Paine, T. Perham, S. Thomas","doi":"10.1109/GAASRW.2003.183769","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183769","url":null,"abstract":"Abstract We have used high-resolution transmission electron microscopy (HRTEM), with focused-ion-beam preparation of foils, to study InP HBT devices, both as-fabricated and after aging in life tests. The technology is HRL's G1 process. We found that even after aging for the equivalent of 2 × 107 h under normal operating conditions, the visible damage is extremely benign: the base and emitter contacts are completely intact, there is no evidence of significant Au or Pt migration into the semiconductor, and minor crystal disorder that develops does not extend more than 100 nm below the metal–semiconductor interfaces. Except for these regions, the intrinsic devices are completely devoid of any anomalous features, to within the 0.3 nm resolution limit of the measurements. These observations provide strong evidence that failure mechanisms involving migration of metal from the ohmic contacts, or extended crystal defects, do not limit the reliability of this technology. The small disorder under the base contacts can probably explain the increases of gain (β) observed early in our life tests, and small increases in the base-collector leakage occurring later in the life tests. The minor disorder under the emitter contacts can probably explain the moderate increase of emitter resistance observed late in our life tests. But the mechanism for the eventual decline in β, observed after a long period of stress, for the equivalent of 107 h of normal operation, is not apparent from the HRTEM images.","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183768
S. Madra
Ab-initio calculations were performed to determine the width of the depletion regions in a n-GalnF‘/p GaAs heterojunction bipolar transistor (HBT), by constructing the energy band diagmms for the GalnP emitter, and the ‘degenerate’ pdoped GaAs base region. The depletion regions were established as the regions of primary heat generation inside the HBT. A detailed thermal model of a 2pm x 16.5pm emitter device with six emitters has been developed using Finite Difference Analysis (FDA). Carc has been taken to incorporate the contact metallization and fine geometry, including the representative collector and base mesa structures. The thermal conductivity of the materials involved were carefully established as functions of temperature. Additionally, the temperature profile across the active region of the device was characterized using emission spectroscopy. Close agreement was found between the results from the thermal model and physical mcasurements. This paper establishes the rationale for appropriating suitable regions inside the active device as sources for heat generation Joule heat, Thomson heat and Recombinant heat, along with a brief discussion of the causes for their generation.
通过构建GalnP发射极和“简并”掺杂GaAs基极区的能带图，采用Ab-initio计算方法确定了n-GalnF ' /p GaAs异质结双极晶体管(HBT)的耗尽区宽度。耗尽区被确定为高温高温炉内部的初级产热区。利用有限差分分析(FDA)开发了一个2pm x 16.5pm具有六个发射器的发射器装置的详细热模型。Carc被用来结合接触金属化和精细的几何结构，包括代表性的收集器和基座台面结构。所涉及的材料的热导率被仔细地建立为温度的函数。此外，利用发射光谱对器件有源区域的温度分布进行了表征。热模型的结果与物理测量结果非常吻合。本文建立了在有源器件内部适当区域作为热源产生焦耳热、汤姆逊热和重组热的基本原理，并简要讨论了它们产生的原因。
{"title":"Role of carrier depletion effects and material properties in advanced microscale thermal modeling of GalnP/pGaAs heterojunction bipolar transistor (HBT) devices","authors":"S. Madra","doi":"10.1109/GAASRW.2003.183768","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183768","url":null,"abstract":"Ab-initio calculations were performed to determine the width of the depletion regions in a n-GalnF‘/p GaAs heterojunction bipolar transistor (HBT), by constructing the energy band diagmms for the GalnP emitter, and the ‘degenerate’ pdoped GaAs base region. The depletion regions were established as the regions of primary heat generation inside the HBT. A detailed thermal model of a 2pm x 16.5pm emitter device with six emitters has been developed using Finite Difference Analysis (FDA). Carc has been taken to incorporate the contact metallization and fine geometry, including the representative collector and base mesa structures. The thermal conductivity of the materials involved were carefully established as functions of temperature. Additionally, the temperature profile across the active region of the device was characterized using emission spectroscopy. Close agreement was found between the results from the thermal model and physical mcasurements. This paper establishes the rationale for appropriating suitable regions inside the active device as sources for heat generation Joule heat, Thomson heat and Recombinant heat, along with a brief discussion of the causes for their generation.","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130103289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183766
P. Cova, D. Gallinari, N. Delmonte, R. Alessi, R. Menozzi
{"title":"Off-state PHEMT breakdown: a temperature-dependent analysis","authors":"P. Cova, D. Gallinari, N. Delmonte, R. Alessi, R. Menozzi","doi":"10.1109/GAASRW.2003.183766","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183766","url":null,"abstract":"","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114364241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183767
Hou-Kuei Huang, C. Wang, Yeong-Her Wang
The influence of the hot electron accelerated stress on DC characteristics of AIGaAsfInGaAsfGaAs pseudomorphic high electron mobility transistors (PIIEMT's) is found to be related to the Schottky characteristics. The studies of reverse Schottky characteristics before and after stress are presented and found to be related to the following two major mechanisms: ( I ) the widening of the depletion under the gate atter stress; (2) the influence of the camers trapping under the gate after stress, which is mainly due to DX-centers. A new model based on the image force of Schottky barrier on hot electrons effects on leakage gate current is proposed. Both AlGaAs and InGaP PHEMT's with the extreme small variation of miniinutn noise figure and associated power gain measured at 12 GHz under hot electron accelerated stress will be investigated. Comparing the noise perfonnance of AIGaAs PHEMT's wilh InGaP PHEMT's, the higher reliability in ItiGaP low noise PHEMT's will be demonstrated.
{"title":"Hot electron effects on AlGaAs/InGaAs/GaAs PHEMT's under accelerated DC stresses and comparison with InGaP PHEMT's","authors":"Hou-Kuei Huang, C. Wang, Yeong-Her Wang","doi":"10.1109/GAASRW.2003.183767","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183767","url":null,"abstract":"The influence of the hot electron accelerated stress on DC characteristics of AIGaAsfInGaAsfGaAs pseudomorphic high electron mobility transistors (PIIEMT's) is found to be related to the Schottky characteristics. The studies of reverse Schottky characteristics before and after stress are presented and found to be related to the following two major mechanisms: ( I ) the widening of the depletion under the gate atter stress; (2) the influence of the camers trapping under the gate after stress, which is mainly due to DX-centers. A new model based on the image force of Schottky barrier on hot electrons effects on leakage gate current is proposed. Both AlGaAs and InGaP PHEMT's with the extreme small variation of miniinutn noise figure and associated power gain measured at 12 GHz under hot electron accelerated stress will be investigated. Comparing the noise perfonnance of AIGaAs PHEMT's wilh InGaP PHEMT's, the higher reliability in ItiGaP low noise PHEMT's will be demonstrated.","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183773
G. Verzellesi, A. Mazzanti, C. Canali, G. Meneghesso, A. Chini, E. Zanoni
Deep-level-induced dc-to-RF dispersion effects, such as gate lag, transconductance (g,) frequency dispersion, and drain-current (Io) collapse, continue to represent a serious limitation for many power microwave FETs based on compound semiconductors, principally because of the associated depadation of output-power density at operating frequencies. Io devices with optimized vertical structure growth, dispersion effects, ifpresent, are induced by deep-level traps at the ungated device surface. The influence of surface traps can actually be minimized by reducing gate-recess extension and/or inter-electrode spacings, but, in doing so, a penalty must be accepted in terms of gate-drain breakdown voltage reduction, the inherent trade-off between de-to-RF dispersion immunity and high-voltage capability making the physical comprehension of dispersion effects crucial for proper procesddevice optimization. Unfortunately, in spite of extensive research efforts, the physics underlying surface-trap action has not been completely clarified yet. The explanation which is more conventionally accepted is that electrons leaking from the gate metal are trappedldetrapped by surface deep levels. Initially proposed for GaAs MESFETs [I], this explanation has been extended to other 111-V FETs [2,3] and, more recently, adopted for GaN-based devices [4]. In ihepveseni work a consisieni sei ofrxperirnental and numerical resulrs ure prrsenied, addressing dc-io-RF dispersion erecis in FETS of two direreeni iechnologies, naniely AIGaAdGaAs lreierosiructure FETs (HFETs) and AIGoN/GuN IIEMTs. Numerical device siniirlations siimesi ihni, d~erenrlyfrom whui coninronl~~ assured. suiface 1rap.s can hehuve. during the switching iransienis of hoih device i.vpes, as hole irups inierading with holes aifracted a! the ungated surfice by surface band bending. Devices used for this work are I ) double recess, doped-channel AIGaAs/GaAs IlFETs featuring different ungated gate-source and gate-drain recess lengths (ALgl=O, 0.1, 0.23 pm), a gate width of 200 pm and D gate length (L,) that varies with ALgl as L, =0.7-2.ALgl; 2) unpassivated AIGaNGaN HEMTs grown by MOCVD on S i c substrates and characterized by a gate widtWlength of 150pm/O.7pm and by gate-source and gate-drain spacings of 0.7 pm and 2 pm, respectively. As far as the AIGaAdGaAs HFETs are concerned, obtained results can be outlined as follows. 1) Gate lag, Io collapse under pulsed-Vos operation, and transconductance (g,,,) frequency dispersion are negligible in samples having ALgl=O, while they increasingly affect device operation at increasing ALgl. This Fdct indicates that deep levels responsible for the observed dispersion effects are located at the ungated recess surface. 2) Gate lag depends markedly on the adopted rum-off VGs value (V,s.o,,) and drain bias (VDD). More specifically, gate-lag effects diminish (i) by making Vos.ovF less negative and (ii) by increasing VDo, see Fig. 1. 3) Temperature (T) impacts gate lag differently
{"title":"Study on the origin of dc-to-RF dispersion effects in GaAs- and GaN-based beterostructure FETs","authors":"G. Verzellesi, A. Mazzanti, C. Canali, G. Meneghesso, A. Chini, E. Zanoni","doi":"10.1109/GAASRW.2003.183773","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183773","url":null,"abstract":"Deep-level-induced dc-to-RF dispersion effects, such as gate lag, transconductance (g,) frequency dispersion, and drain-current (Io) collapse, continue to represent a serious limitation for many power microwave FETs based on compound semiconductors, principally because of the associated depadation of output-power density at operating frequencies. Io devices with optimized vertical structure growth, dispersion effects, ifpresent, are induced by deep-level traps at the ungated device surface. The influence of surface traps can actually be minimized by reducing gate-recess extension and/or inter-electrode spacings, but, in doing so, a penalty must be accepted in terms of gate-drain breakdown voltage reduction, the inherent trade-off between de-to-RF dispersion immunity and high-voltage capability making the physical comprehension of dispersion effects crucial for proper procesddevice optimization. Unfortunately, in spite of extensive research efforts, the physics underlying surface-trap action has not been completely clarified yet. The explanation which is more conventionally accepted is that electrons leaking from the gate metal are trappedldetrapped by surface deep levels. Initially proposed for GaAs MESFETs [I], this explanation has been extended to other 111-V FETs [2,3] and, more recently, adopted for GaN-based devices [4]. In ihepveseni work a consisieni sei ofrxperirnental and numerical resulrs ure prrsenied, addressing dc-io-RF dispersion erecis in FETS of two direreeni iechnologies, naniely AIGaAdGaAs lreierosiructure FETs (HFETs) and AIGoN/GuN IIEMTs. Numerical device siniirlations siimesi ihni, d~erenrlyfrom whui coninronl~~ assured. suiface 1rap.s can hehuve. during the switching iransienis of hoih device i.vpes, as hole irups inierading with holes aifracted a! the ungated surfice by surface band bending. Devices used for this work are I ) double recess, doped-channel AIGaAs/GaAs IlFETs featuring different ungated gate-source and gate-drain recess lengths (ALgl=O, 0.1, 0.23 pm), a gate width of 200 pm and D gate length (L,) that varies with ALgl as L, =0.7-2.ALgl; 2) unpassivated AIGaNGaN HEMTs grown by MOCVD on S i c substrates and characterized by a gate widtWlength of 150pm/O.7pm and by gate-source and gate-drain spacings of 0.7 pm and 2 pm, respectively. As far as the AIGaAdGaAs HFETs are concerned, obtained results can be outlined as follows. 1) Gate lag, Io collapse under pulsed-Vos operation, and transconductance (g,,,) frequency dispersion are negligible in samples having ALgl=O, while they increasingly affect device operation at increasing ALgl. This Fdct indicates that deep levels responsible for the observed dispersion effects are located at the ungated recess surface. 2) Gate lag depends markedly on the adopted rum-off VGs value (V,s.o,,) and drain bias (VDD). More specifically, gate-lag effects diminish (i) by making Vos.ovF less negative and (ii) by increasing VDo, see Fig. 1. 3) Temperature (T) impacts gate lag differently","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123402478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183771
K. Feng, N. Nguyen, C. Nguyen
Abstrad In this paper, we demonstrated that with our proprietary device design and process technology, GCS’s InP HBTs show excellent reliability under high current density lifetests. Both Va. and emitter resistance are very stable during ISOkA/cm’ stressing, which indicates that the Cdoped InP HBT is potentially much more stable compared lo Be-doped InP HBT for high current density operation. No low activation energy (
{"title":"Investigation of reliability for C-doped InP/InGaAs/InP HBTs under high current density operation","authors":"K. Feng, N. Nguyen, C. Nguyen","doi":"10.1109/GAASRW.2003.183771","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183771","url":null,"abstract":"Abstrad In this paper, we demonstrated that with our proprietary device design and process technology, GCS’s InP HBTs show excellent reliability under high current density lifetests. Both Va. and emitter resistance are very stable during ISOkA/cm’ stressing, which indicates that the Cdoped InP HBT is potentially much more stable compared lo Be-doped InP HBT for high current density operation. No low activation energy (<O.SeV) failure mode was found for out C-doped InP HBTs. The extracted activation energy is greater than 0.97eV. The estimated MTTF at 125°C is over 3 million hours for device operating at 150kAicmz current density.","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128093319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183772
Y. Chou, I. Smorchkova, D. Leung, M. Wojitowicz, R. Grundbacher, L. Callejo, O. Kan, R. Lai, Po-Hsin Liu, D. Eng, R. Tsai, A. Oki
Reliability investigation was performed on 0.25 pin AIGaN/GaN HEMTs grown by MOCVD on 2-inch SIC substrates. The devices were fabricated using Northrop Gruminan Space Technology’s (NGST) AlGaNlGaN HEMTs process technology. A temperature step stress (starting at 150°C with a step of 15°C; ending at 240°C; 48 hrs for each temperature cycle) was employed for the quick reliability evaluation of AIGaN/CiaN HEMTs. It was found that the degradation of AlGaN/GaN HEMTs was initiated at junction temperature of 345°C. The degradation characteristics consist of a decrease of drain current and transconductance? and an increase of channel-onresistance. However, there is no noticeable degradation of the gate diode (ideality factor, barrier height, and reverse gate leakage current). The FIB/STEM technique was used to examine the degraded devices. There is no detectable ohmic metal or gate metal interdiffusion into the epitaxial materials from STEM. Accordingly, the degradation inechanism of AIGaN/GaN HEMTs under elevated temperature lifctesting is different from the degradation mechanisms observed in GaAs PHEMTs and InP HEMTs. The reliability performance was also compared between two vendors of AIGaN/GaN epilayers. The results show that the reliability of AIGaN/GaN HEMTs could strongly depend on the material quality of AlGaN/GaN epitaxial layers on SIC substrates. been demonstrated at 10 GHz [I]. AIGaNIGaN
{"title":"Reliability investigation of 0.25 /spl mu/m AlGaN/GaN HEMTs under elevated temperature lifetesting","authors":"Y. Chou, I. Smorchkova, D. Leung, M. Wojitowicz, R. Grundbacher, L. Callejo, O. Kan, R. Lai, Po-Hsin Liu, D. Eng, R. Tsai, A. Oki","doi":"10.1109/GAASRW.2003.183772","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183772","url":null,"abstract":"Reliability investigation was performed on 0.25 pin AIGaN/GaN HEMTs grown by MOCVD on 2-inch SIC substrates. The devices were fabricated using Northrop Gruminan Space Technology’s (NGST) AlGaNlGaN HEMTs process technology. A temperature step stress (starting at 150°C with a step of 15°C; ending at 240°C; 48 hrs for each temperature cycle) was employed for the quick reliability evaluation of AIGaN/CiaN HEMTs. It was found that the degradation of AlGaN/GaN HEMTs was initiated at junction temperature of 345°C. The degradation characteristics consist of a decrease of drain current and transconductance? and an increase of channel-onresistance. However, there is no noticeable degradation of the gate diode (ideality factor, barrier height, and reverse gate leakage current). The FIB/STEM technique was used to examine the degraded devices. There is no detectable ohmic metal or gate metal interdiffusion into the epitaxial materials from STEM. Accordingly, the degradation inechanism of AIGaN/GaN HEMTs under elevated temperature lifctesting is different from the degradation mechanisms observed in GaAs PHEMTs and InP HEMTs. The reliability performance was also compared between two vendors of AIGaN/GaN epilayers. The results show that the reliability of AIGaN/GaN HEMTs could strongly depend on the material quality of AlGaN/GaN epitaxial layers on SIC substrates. been demonstrated at 10 GHz [I]. AIGaNIGaN","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127920207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183765
H. Saigusa, A. Malik, L. Rushing, F. Gao
In today’s highly competitive semiconductor IC market, it is critical to address the market requirements of low cost, superb performance, and high reliability for the success of any product. It becomes increasingly challenging to meet these requirements that sometimes conflict with each other. Skyworks recently developed a third generation pseudomorphic high electron mobility transistor (PHEMT) process with reduced gate pitch and ohmic width geometry to increase the FET density factor. While this initiative significantly improves the throughput, we have launched a series of reliability experiments to assess the possible impacts on device reliability. Potential issues include greater leakage, smaller breakdown voltage, and hotter channel under the same electrical bias conditions.
{"title":"Reliability lifetest on etch-stop 0.5-/spl mu/m PHEMT with reduced gate pitch and ohmic width geometry","authors":"H. Saigusa, A. Malik, L. Rushing, F. Gao","doi":"10.1109/GAASRW.2003.183765","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183765","url":null,"abstract":"In today’s highly competitive semiconductor IC market, it is critical to address the market requirements of low cost, superb performance, and high reliability for the success of any product. It becomes increasingly challenging to meet these requirements that sometimes conflict with each other. Skyworks recently developed a third generation pseudomorphic high electron mobility transistor (PHEMT) process with reduced gate pitch and ohmic width geometry to increase the FET density factor. While this initiative significantly improves the throughput, we have launched a series of reliability experiments to assess the possible impacts on device reliability. Potential issues include greater leakage, smaller breakdown voltage, and hotter channel under the same electrical bias conditions.","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130602194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/GAASRW.2003.183770
W. Roesch, S. Jittinorasett
Flip Chip assembly offers a reliable, sinall footprint, thermally enhanced alternative to wire bonding. New copper ‘bumps”increase Flip Chip advantages for GaAs devices. This study will address failure mechanisms accelerated by thermal excursions for new copper bumps. Thermal excursion mechanisms are ones accelerated by temperature cycling, thcnnal shock, simulation of assembly reflow or power cycling.[i J
{"title":"Investigating thermal excursion failure mechanisms for flip chip","authors":"W. Roesch, S. Jittinorasett","doi":"10.1109/GAASRW.2003.183770","DOIUrl":"https://doi.org/10.1109/GAASRW.2003.183770","url":null,"abstract":"Flip Chip assembly offers a reliable, sinall footprint, thermally enhanced alternative to wire bonding. New copper ‘bumps”increase Flip Chip advantages for GaAs devices. This study will address failure mechanisms accelerated by thermal excursions for new copper bumps. Thermal excursion mechanisms are ones accelerated by temperature cycling, thcnnal shock, simulation of assembly reflow or power cycling.[i J","PeriodicalId":431077,"journal":{"name":"Proceedings GaAs Reliability Workshop, 2003.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121908218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：