Yang-Kyu Choi, Yoo-Chan Jeon, P. Ranade, H. Takenuchi, T. King, J. Bokor, C. Hu
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引用次数: 26
Abstract
MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.
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