A low-noise local bitline technique for dual-Vt register files

Abstract

A low-noise local bitline technique is presented for dual-Vt register files. The proposed read port topology produces an equal magnitude of local bitline (LBL) leakage currents during standby and read `0¿ modes of operation. This feature allows a standard keeper to operate more effectively at reduced supply voltages due to suppressed LBL noise and permits robust memory operation down to data retention voltage (DRV). The LBL noise at DRV is reduced to 34.7% of the permitted noise level. Furthermore, LBL leakage currents are suppressed by 39.4% and 93.5% in standby and read `0¿ modes of operation with the proposed technique as compared to the conventional LBL technique under an equal LBL delay and robustness constraint. These benefits are achieved at the expense of 35.3% increase in bitcell area, 5.3% increase in energy consumption in a read operation and 14.5% degradation in the overall read delay.