Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828600
S. Ordas, Mathieu Carbone, G. Ducharme, S. Tiran, P. Maurine
The use of Dynamic Voltage and Frequency Scaling technique (DVFS) in Systems-on-Chip is becoming more and more common. This technique, re-named RDVFS for the occasion, has recently been proposed as a countermeasure against Side Channel Attacks (SCA) through the randomization of the choices of V and F, at the expense of power consumption. In this paper, theoretical and practical assessments of the robustness against Correlation Power Analysis (CPA) of the RDVFS countermeasure is proposed.
{"title":"Efficiency of the RDVFS countermeasure","authors":"S. Ordas, Mathieu Carbone, G. Ducharme, S. Tiran, P. Maurine","doi":"10.1109/FTFC.2014.6828600","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828600","url":null,"abstract":"The use of Dynamic Voltage and Frequency Scaling technique (DVFS) in Systems-on-Chip is becoming more and more common. This technique, re-named RDVFS for the occasion, has recently been proposed as a countermeasure against Side Channel Attacks (SCA) through the randomization of the choices of V and F, at the expense of power consumption. In this paper, theoretical and practical assessments of the robustness against Correlation Power Analysis (CPA) of the RDVFS countermeasure is proposed.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828612
A. Kushnerov
The paper proposes a new class of dual output step-up Fibonacci switched capacitor converters (SCC) and formal approach for its synthesis. The resolution of target voltages in the new SCC has been significantly increased in comparison with the previously developed single-output SCC, where the target voltages are spaced as 1/x. In the case of three flying capacitors the proposed SCC provides six different pairs of target voltages. The output current in the proposed SCC is discontinuous due to the switching between three states over a period. This operation mode is called sub-period interleaving and may help lower the output voltage ripple. The proposed SCC can be used in low-voltage energy harvesting devices and/or in VLSI systems to provide different voltages to different parts of chip. The presented results were verified experimentally.
{"title":"Dual output sub-period interleaved step-up Fibonacci switched capacitor converters","authors":"A. Kushnerov","doi":"10.1109/FTFC.2014.6828612","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828612","url":null,"abstract":"The paper proposes a new class of dual output step-up Fibonacci switched capacitor converters (SCC) and formal approach for its synthesis. The resolution of target voltages in the new SCC has been significantly increased in comparison with the previously developed single-output SCC, where the target voltages are spaced as 1/x. In the case of three flying capacitors the proposed SCC provides six different pairs of target voltages. The output current in the proposed SCC is discontinuous due to the switching between three states over a period. This operation mode is called sub-period interleaving and may help lower the output voltage ripple. The proposed SCC can be used in low-voltage energy harvesting devices and/or in VLSI systems to provide different voltages to different parts of chip. The presented results were verified experimentally.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129751257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828601
Mehmet Ince, Feyyaz Melih Akcakaya, G. Dundar
This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18 μm technology. It consumes 7.25 μW for 15 bit Audio ΣΔ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth.
{"title":"A 7.3 μW decimation filter for 15 bit 25 kHz audio ΣΔ modulator","authors":"Mehmet Ince, Feyyaz Melih Akcakaya, G. Dundar","doi":"10.1109/FTFC.2014.6828601","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828601","url":null,"abstract":"This paper presents a low power decimation filter designed for oversampling ΣΔ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18 μm technology. It consumes 7.25 μW for 15 bit Audio ΣΔ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128348062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828594
Ryo Umesao, J. Ida, Masanari Mabuchi, Yuta Kunori, Sou Tashino, Takayuki Mori, H. Miyagoshi, K. Noguchi, K. Itoh
Gate controlled diodes (GCD) and rectifiers using the GCD with the different threshold voltage (Vt) of the MOS by the ion-implantation were fabricated with 0.18 um CMOS technology. The DC characterization of the GCD revealed that the turn on voltage of the GCD is reduced and becomes lower than the Schottky Barrier Diode (SBD) when the Vt of the MOS is reduced and there exist the bulk leakage pass of the MOS on the reverse leakage current of the 0.18 um GCD. It was also clarified that the parasitic capacitance of the GCD will be lower than the SBD. From simulations and measurements of the rectifier, it was found out for the first time that the rectification efficiency of the rectifier using the GCD has a peak value when changing the Vt of MOS in the GCD, and the rectification efficiency of the rectifier using the GCD with the near zero Vt of the MOS overcomes the rectifier' using the specially designed SBD for the small signal applications, on the ultralow power input of the RF energy harvesting.
采用0.18 um CMOS工艺制备了具有不同MOS阈值电压(Vt)的栅极控制二极管(GCD)和整流器。对GCD的直流特性分析表明，当MOS的Vt降低，且在0.18 um GCD的反向漏电流上存在MOS的体漏通时，GCD的导通电压降低并低于肖特基势垒二极管(SBD)。此外，还澄清了GCD的寄生电容将低于SBD。通过对整流器的仿真和测量，首次发现采用GCD整流器的整流效率在改变GCD中MOS的Vt时出现峰值，并且在MOS Vt接近于零的情况下，采用GCD整流器的整流效率优于采用专门为小信号应用而设计的SBD整流效率，在射频能量收集的超低功率输入下。
{"title":"High efficiency RF energy harvesting with threshold-votlage-adjusted gate control diode","authors":"Ryo Umesao, J. Ida, Masanari Mabuchi, Yuta Kunori, Sou Tashino, Takayuki Mori, H. Miyagoshi, K. Noguchi, K. Itoh","doi":"10.1109/FTFC.2014.6828594","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828594","url":null,"abstract":"Gate controlled diodes (GCD) and rectifiers using the GCD with the different threshold voltage (Vt) of the MOS by the ion-implantation were fabricated with 0.18 um CMOS technology. The DC characterization of the GCD revealed that the turn on voltage of the GCD is reduced and becomes lower than the Schottky Barrier Diode (SBD) when the Vt of the MOS is reduced and there exist the bulk leakage pass of the MOS on the reverse leakage current of the 0.18 um GCD. It was also clarified that the parasitic capacitance of the GCD will be lower than the SBD. From simulations and measurements of the rectifier, it was found out for the first time that the rectification efficiency of the rectifier using the GCD has a peak value when changing the Vt of MOS in the GCD, and the rectification efficiency of the rectifier using the GCD with the near zero Vt of the MOS overcomes the rectifier' using the specially designed SBD for the small signal applications, on the ultralow power input of the RF energy harvesting.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114634239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828596
E. Kussener, J. Aguilar, O. Mainard, D. Goguenheim, G. Oudinet, P. Salin, C. Forni
A large number of solutions on electrostimulation were proposed in the last twenty years with the aim of looking after certain pathologies. They rely on the principle that electrostimulation of a neuron, muscle or another internal nerve is possible. In this context, this paper presents a solution of deep brain stimulator (DBS) having for aim to reduce the influence of the Parkinson's disease. This paper presents monophasic and biphasic electrostimulation topologies. The integrated system on chip solution was developped on 0.35¿m standard CMOS technology. The silicon die possesses a size of 620x550¿m2, with an improved battery life of about a week (ten times longer than the discrete version). The circuit has two terminals directly connected on the brain via two electrodes and two terminals to be connected to the coin cell battery (the only non under cutaneous part).
{"title":"Implantable electrostimulation system in freely moving rodent for DBS treatment","authors":"E. Kussener, J. Aguilar, O. Mainard, D. Goguenheim, G. Oudinet, P. Salin, C. Forni","doi":"10.1109/FTFC.2014.6828596","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828596","url":null,"abstract":"A large number of solutions on electrostimulation were proposed in the last twenty years with the aim of looking after certain pathologies. They rely on the principle that electrostimulation of a neuron, muscle or another internal nerve is possible. In this context, this paper presents a solution of deep brain stimulator (DBS) having for aim to reduce the influence of the Parkinson's disease. This paper presents monophasic and biphasic electrostimulation topologies. The integrated system on chip solution was developped on 0.35¿m standard CMOS technology. The silicon die possesses a size of 620x550¿m2, with an improved battery life of about a week (ten times longer than the discrete version). The circuit has two terminals directly connected on the brain via two electrodes and two terminals to be connected to the coin cell battery (the only non under cutaneous part).","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125739900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828618
B. Mohammadi, O. Andersson, P. Meinerzhagen, Y. Sherazi, A. Burg, J. Rodrigues
The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power.
{"title":"A 0.28-0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS","authors":"B. Mohammadi, O. Andersson, P. Meinerzhagen, Y. Sherazi, A. Burg, J. Rodrigues","doi":"10.1109/FTFC.2014.6828618","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828618","url":null,"abstract":"The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129702694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828619
A. Gaume, F. Vialatte, G. Dreyfus
In this paper, we address the problem of detecting steady-state visual evoked potentials (SSVEPs) in EEG signals by using a set of simulated trains of VEPs instead of the sine-waves basis typically used in Fourier Transform. The detection algorithm is calibrated using the subject's brain response to visual stimulation. The original contribution of the paper is that our detection method automatically takes into account all the spectral content adapted to the steady-state response in terms of harmonic localization, weights, and phase. We show that this method give better results than simple frequency analysis for SSVEP detection while requiring less features, thereby reducing the risk of overfitting the detection model.
{"title":"Detection of steady-state visual evoked potentials using simulated trains of transient evoked potentials","authors":"A. Gaume, F. Vialatte, G. Dreyfus","doi":"10.1109/FTFC.2014.6828619","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828619","url":null,"abstract":"In this paper, we address the problem of detecting steady-state visual evoked potentials (SSVEPs) in EEG signals by using a set of simulated trains of VEPs instead of the sine-waves basis typically used in Fourier Transform. The detection algorithm is calibrated using the subject's brain response to visual stimulation. The original contribution of the paper is that our detection method automatically takes into account all the spectral content adapted to the steady-state response in terms of harmonic localization, weights, and phase. We show that this method give better results than simple frequency analysis for SSVEP detection while requiring less features, thereby reducing the risk of overfitting the detection model.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127465255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828611
Hraziia, A. Amara, A. Vladimirescu, C. Anghel, O. Thomas
A novel hybrid memory architecture - Non-Volatile SRAMs (NVSRAMs) wherein resistive memories incorporated as an integral part of SRAM cell to provide information back-up feature is presented in this paper. It also makes a discussion on some of the challenges faced in implementing hybrid memories and the prospective solutions.
{"title":"Design challenges and solutions for Non-Volatile SRAMs","authors":"Hraziia, A. Amara, A. Vladimirescu, C. Anghel, O. Thomas","doi":"10.1109/FTFC.2014.6828611","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828611","url":null,"abstract":"A novel hybrid memory architecture - Non-Volatile SRAMs (NVSRAMs) wherein resistive memories incorporated as an integral part of SRAM cell to provide information back-up feature is presented in this paper. It also makes a discussion on some of the challenges faced in implementing hybrid memories and the prospective solutions.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828608
D. Sokolov, A. Mokhov, A. Yakovlev, D. Lloyd
Power management is an important part of modern microelectronics, however, the possibilities for its design automation are insufficiently studied and therefore the state-of-the-art synthesis methods produce suboptimal power control circuits. Currently the same design principles, which are based on synthesis of synchronous state machines, are used for both the data processing components and the power control circuits. While the synchronous operation is natural for data processing, it does not meet the low-latency and resilience requirements imposed by the power control logic. We believe that design of power control requires a fundamentally different approach based on clock-less design principles, which are characterised by robust operation in variable conditions and high responsiveness to the input stimuli. One of the main obstacles on this pathway is the difficulty of expressing the intended power control behaviour in a formal and unambiguous form which can be subsequently used for logic synthesis and verification of the obtained solution.
{"title":"Towards asynchronous power management","authors":"D. Sokolov, A. Mokhov, A. Yakovlev, D. Lloyd","doi":"10.1109/FTFC.2014.6828608","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828608","url":null,"abstract":"Power management is an important part of modern microelectronics, however, the possibilities for its design automation are insufficiently studied and therefore the state-of-the-art synthesis methods produce suboptimal power control circuits. Currently the same design principles, which are based on synthesis of synchronous state machines, are used for both the data processing components and the power control circuits. While the synchronous operation is natural for data processing, it does not meet the low-latency and resilience requirements imposed by the power control logic. We believe that design of power control requires a fundamentally different approach based on clock-less design principles, which are characterised by robust operation in variable conditions and high responsiveness to the input stimuli. One of the main obstacles on this pathway is the difficulty of expressing the intended power control behaviour in a formal and unambiguous form which can be subsequently used for logic synthesis and verification of the obtained solution.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-04DOI: 10.1109/FTFC.2014.6828605
Hong Zhang, Dong Li, Qing Wang, Jie Zhang, Chong Li, Ruizhi Zhang
A resistor-less bandgap reference (BGR) for ultra-low power large-scale integrations (LSIs) is proposed in this paper. The BGR consists of a nano-ampere current reference circuit, a complementary-to-absolute-temperature (CTAT) voltage generator based on a diode connected MOSFET operating in subthreshold region, and a proportional-to-absolute-temperature (PTAT) voltage generator. A new topology that combines two mechanisms to generate PTAT voltage is proposed for the first stage of the PTAT generator, which can achieve higher slope in the voltage-temperature characteristics. Therefore, only 3 sub-stages are required in the PTAT generator, and both power dissipation and chip area can be reduced. The BGR is designed in a 0.35-μm CMOS process. Simulated results show that the BGR achieves a 1.1-V reference voltage with best temperature coefficient of 35 ppm/°C, while consuming only 40-nA under a 3.3 V power supply.
{"title":"A resistor-less bandgap reference with improved PTAT generator for ultra-low-power LSIs","authors":"Hong Zhang, Dong Li, Qing Wang, Jie Zhang, Chong Li, Ruizhi Zhang","doi":"10.1109/FTFC.2014.6828605","DOIUrl":"https://doi.org/10.1109/FTFC.2014.6828605","url":null,"abstract":"A resistor-less bandgap reference (BGR) for ultra-low power large-scale integrations (LSIs) is proposed in this paper. The BGR consists of a nano-ampere current reference circuit, a complementary-to-absolute-temperature (CTAT) voltage generator based on a diode connected MOSFET operating in subthreshold region, and a proportional-to-absolute-temperature (PTAT) voltage generator. A new topology that combines two mechanisms to generate PTAT voltage is proposed for the first stage of the PTAT generator, which can achieve higher slope in the voltage-temperature characteristics. Therefore, only 3 sub-stages are required in the PTAT generator, and both power dissipation and chip area can be reduced. The BGR is designed in a 0.35-μm CMOS process. Simulated results show that the BGR achieves a 1.1-V reference voltage with best temperature coefficient of 35 ppm/°C, while consuming only 40-nA under a 3.3 V power supply.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125935802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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