SI architecture optimized high speed serial design for PCB cost saving

Abstract

As integrated circuit (IC) chips keep growing in size, I/O data rates and complexity, electrical margin left on printed circuit board (PCB) gets smaller. Mid-loss or even low-loss material may be needed in more cases to meet high speed (HS) signal routing length requests, which leads to cost-adder on PCB. This submission introduces analysis flow as well as practical methods targeting reducing PCB material cost through SI architecture optimization. Following the analysis flow, board designers can get better opportunity of using cheaper material without sacrificing performance.