Novel Push-Push Frequency Doubler Concept

S. Vehring, G. Boeck
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引用次数: 1

Abstract

This paper presents a novel push-push frequency doubler concept which can deliver high balanced output power. Two lumped couplers provide balanced quadrature input signaling for two doubler cells. As a result, the output signals of the two doubler cells form an inherently balanced output and a lossy output transformer can be avoided. Hence, higher output power and efficiency can be achieved. Moreover, high fundamental rejection and supply suppression with low LO leakage into other circuit blocks are further advantages. As a proof of concept, a K-band doubler is implemented in a 65 nm CMOS technology. At 0 dBm input power, the circuit delivers 4.3 dBm output power with more than 6 % PAE. The chip draws 24 mA from a 1.2 V supply and the total chip area is 0.85 × 0.55 mm2, The fundamental suppression is around 44 dBc. The concept is applicable to other technologies and frequencies as well.
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新颖的推推式倍频器概念
本文提出了一种新颖的推推式倍频器的概念,可以提供高平衡的输出功率。两个集总耦合器为两个倍频单元提供平衡的正交输入信号。因此,两个倍频单元的输出信号形成一个固有的平衡输出,并且可以避免损耗输出变压器。因此,可以实现更高的输出功率和效率。此外,高基波抑制和低LO泄漏到其他电路块的电源抑制是进一步的优势。作为概念验证,k波段倍频器在65纳米CMOS技术中实现。在输入功率为0 dBm时,电路输出功率为4.3 dBm, PAE大于6%。该芯片从1.2 V电源中吸取24 mA,芯片总面积为0.85 × 0.55 mm2,基波抑制约为44 dBc。这个概念也适用于其他技术和频率。
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