Hybrid reconfigurable processors-the road to low-power consumption

Abstract

Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becoming more and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this paper, the opportunity for substantial power reduction by using hybrid reconfigurable processors is explored. With the aid of a number of small benchmarks, it is demonstrated that power reductions of orders of magnitude are attainable.