An Electrical Inline-Testable Structure to Monitor Gate-Source/Drain Short Defect Caused by Imperfect Fin-Cut Patterning in FinFET Technology

Abstract

On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.