System level interconnect power modeling

Abstract

While power consumption of interconnects has become an important issue as technology scales, very few papers on power modeling of interconnects are available in the literature. This paper presents an architectural level interconnect power modeling method and applies it to a commercial chip that integrates a 16-bit DSP and a 32-bit RISC microcontroller. This power modeling method is applicable to any architecture if an architectural level description is provided. An architectural level simulator based on the commercial chip has been enhanced to generate the activity parameters for several signal processing benchmarks and some simple synthetic benchmarks at different technology feature sizes. The power measurements for all six global buses of the chip are reported.